From 45e8a1d2d8b26165156b972e5a629c52408f65e9 Mon Sep 17 00:00:00 2001 From: Asutosh Das Date: Fri, 10 Apr 2020 15:43:45 -0700 Subject: [PATCH] phy: ufs-qcom: Update offsets for Lahaina Updates few offsets for Lahaina phy. Change-Id: Ifec289dbe12e85e9f8e73f91310198aa6ff75676 Signed-off-by: Asutosh Das --- .../qualcomm/phy-qcom-ufs-qmp-v4-lahaina.c | 2 ++ .../qualcomm/phy-qcom-ufs-qmp-v4-lahaina.h | 26 ++++++++++--------- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-lahaina.c b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-lahaina.c index adb5ab39127a..c7fc9e527351 100644 --- a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-lahaina.c +++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-lahaina.c @@ -235,6 +235,8 @@ static void ufs_qcom_phy_qmp_v4_dbg_register_dump(struct ufs_qcom_phy *phy) { ufs_qcom_phy_dump_regs(phy, COM_BASE, COM_SIZE, "PHY QSERDES COM Registers "); + ufs_qcom_phy_dump_regs(phy, PCS2_BASE, PCS2_SIZE, + "PHY PCS2 Registers "); ufs_qcom_phy_dump_regs(phy, PHY_BASE, PHY_SIZE, "PHY Registers "); ufs_qcom_phy_dump_regs(phy, RX_BASE(0), RX_SIZE, diff --git a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-lahaina.h b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-lahaina.h index aa1ab7c332c0..83ecdb01d83d 100644 --- a/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-lahaina.h +++ b/drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4-lahaina.h @@ -13,8 +13,10 @@ #define COM_SIZE 0x1C0 #define PHY_BASE 0xC00 #define PHY_SIZE 0x200 +#define PCS2_BASE 0x200 +#define PCS2_SIZE 0x40 #define TX_BASE(n) (0x400 + (0x400 * n)) -#define TX_SIZE 0x16C +#define TX_SIZE 0x188 #define RX_BASE(n) (0x600 + (0x400 * n)) #define RX_SIZE 0x200 #define COM_OFF(x) (COM_BASE + x) @@ -73,24 +75,24 @@ #define UFS_PHY_RX_SIGDET_CTRL1 PHY_OFF(0x154) /* UFS PHY TX registers */ -#define QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1 TX_OFF(0, 0xD8) -#define QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1 TX_OFF(0, 0xDC) -#define QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1 TX_OFF(0, 0xE0) -#define QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1 TX_OFF(0, 0xE4) +#define QSERDES_TX0_PWM_GEAR_1_DIVIDER_BAND0_1 TX_OFF(0, 0x178) +#define QSERDES_TX0_PWM_GEAR_2_DIVIDER_BAND0_1 TX_OFF(0, 0x17C) +#define QSERDES_TX0_PWM_GEAR_3_DIVIDER_BAND0_1 TX_OFF(0, 0x180) +#define QSERDES_TX0_PWM_GEAR_4_DIVIDER_BAND0_1 TX_OFF(0, 0x184) #define QSERDES_TX0_LANE_MODE_1 TX_OFF(0, 0x84) #define QSERDES_TX0_LANE_MODE_3 TX_OFF(0, 0x8C) #define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX TX_OFF(0, 0x3C) #define QSERDES_TX0_RES_CODE_LANE_OFFSET_RX TX_OFF(0, 0x40) #define QSERDES_TX0_TRAN_DRVR_EMP_EN TX_OFF(0, 0xC0) -#define QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1 TX_OFF(1, 0xD8) -#define QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1 TX_OFF(1, 0xDC) -#define QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1 TX_OFF(1, 0xE0) -#define QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1 TX_OFF(1, 0xE4) +#define QSERDES_TX1_PWM_GEAR_1_DIVIDER_BAND0_1 TX_OFF(1, 0x178) +#define QSERDES_TX1_PWM_GEAR_2_DIVIDER_BAND0_1 TX_OFF(1, 0x17C) +#define QSERDES_TX1_PWM_GEAR_3_DIVIDER_BAND0_1 TX_OFF(1, 0x180) +#define QSERDES_TX1_PWM_GEAR_4_DIVIDER_BAND0_1 TX_OFF(1, 0x184) #define QSERDES_TX1_LANE_MODE_1 TX_OFF(1, 0x84) -#define QSERDES_TX1_LANE_MODE_3 TX_OFF(0, 0x8C) -#define QSERDES_TX1_RES_CODE_LANE_OFFSET_TX TX_OFF(0, 0x3C) -#define QSERDES_TX1_RES_CODE_LANE_OFFSET_RX TX_OFF(0, 0x40) +#define QSERDES_TX1_LANE_MODE_3 TX_OFF(1, 0x8C) +#define QSERDES_TX1_RES_CODE_LANE_OFFSET_TX TX_OFF(1, 0x3C) +#define QSERDES_TX1_RES_CODE_LANE_OFFSET_RX TX_OFF(1, 0x40) #define QSERDES_TX1_TRAN_DRVR_EMP_EN TX_OFF(1, 0xC0) /* UFS PHY RX registers */