From fbb224080b7bf4c0388d2b489f061351ba0706f5 Mon Sep 17 00:00:00 2001
From: Wenjun Zhang <c_wjzhan@qti.qualcomm.com>
Date: Fri, 26 Feb 2021 09:39:15 +0800
Subject: [PATCH] ARM: dts: msm: set qupv3 se15 i2c rate to 100khz

Since it was used only for dsi-hdmi bridge chipset,
the chipset could not support higher rate, so set
it to 100khz.

Change-Id: Ieeede3aabb0698270bf0d9eec920c787c11ecf83
---
 qcom/lahaina-hdk.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/qcom/lahaina-hdk.dtsi b/qcom/lahaina-hdk.dtsi
index 1302ac8c52d3..e0c3d0395416 100644
--- a/qcom/lahaina-hdk.dtsi
+++ b/qcom/lahaina-hdk.dtsi
@@ -85,7 +85,9 @@
 
 &qupv3_se15_i2c {
 	status = "ok";
-
+	qcom,clk-freq-out = <100000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
 	lt9611: lt,lt9611@2b {
 		compatible = "lt,lt9611uxc";
 		reg = <0x2b>;