From 8989993edf35acb5b040bfbef6bb86db7196dc90 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Fri, 17 Sep 2021 15:24:28 +0530 Subject: [PATCH] ASoC: wcd937x: Add change for LDOL VOUT accuracy calibration ATE stores the calibration result in EFUSE register. This has to be copied to sleep bandgap voltage for accurate calibration. Change-Id: I118c5c3b42ba4cfd42185d8da6d468f44e31b88f Signed-off-by: Vatsal Bucha --- asoc/codecs/wcd937x/wcd937x.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/asoc/codecs/wcd937x/wcd937x.c b/asoc/codecs/wcd937x/wcd937x.c index 37cf1fd9c64f..30338cb77ecc 100644 --- a/asoc/codecs/wcd937x/wcd937x.c +++ b/asoc/codecs/wcd937x/wcd937x.c @@ -150,8 +150,18 @@ static int wcd937x_handle_post_irq(void *data) static int wcd937x_init_reg(struct snd_soc_component *component) { - snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL, + u32 val =0; + val = snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_29) + & 0x0F; + if (snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16) + == 0x02 || snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_17) > 0x09) { + snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL, + 0x0E, val); + } else { + snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL, 0x0E, 0x0E); + } snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL, 0x80, 0x80); usleep_range(1000, 1010);