From fbf704a3b0d14e16b6fa9887ed94e5bf754207cf Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 19 May 2020 13:08:23 +0530 Subject: [PATCH] bindings: clock: qcom: Update the GPU CC clock IDs Update the clock IDs which are required and supported from the Graphics clock controller on HOLI. Change-Id: I8f16d0ff3ed42500521c8384cd8272ce9d5b9d22 Signed-off-by: Taniya Das --- include/dt-bindings/clock/qcom,gpucc-holi.h | 48 ++++++++------------- 1 file changed, 17 insertions(+), 31 deletions(-) diff --git a/include/dt-bindings/clock/qcom,gpucc-holi.h b/include/dt-bindings/clock/qcom,gpucc-holi.h index a233fc3081ff..9d7a282238e3 100644 --- a/include/dt-bindings/clock/qcom,gpucc-holi.h +++ b/include/dt-bindings/clock/qcom,gpucc-holi.h @@ -7,38 +7,24 @@ #define _DT_BINDINGS_CLK_QCOM_GPU_CC_HOLI_H /* GPU_CC clocks */ -#define GPU_CC_PLL0 0 -#define GPU_CC_PLL1 1 -#define GPU_CC_ACD_AHB_CLK 2 -#define GPU_CC_ACD_CXO_CLK 3 -#define GPU_CC_AHB_CLK 4 -#define GPU_CC_CRC_AHB_CLK 5 -#define GPU_CC_CX_APB_CLK 6 -#define GPU_CC_CX_GFX3D_CLK 7 -#define GPU_CC_CX_GFX3D_SLV_CLK 8 -#define GPU_CC_CX_GMU_CLK 9 -#define GPU_CC_CX_SNOC_DVM_CLK 10 -#define GPU_CC_CXO_AON_CLK 11 -#define GPU_CC_CXO_CLK 12 -#define GPU_CC_GMU_CLK_SRC 13 -#define GPU_CC_GX_CXO_CLK 14 -#define GPU_CC_GX_GFX3D_CLK 15 -#define GPU_CC_GX_GMU_CLK 16 -#define GPU_CC_GX_QDSS_TSCTR_CLK 17 -#define GPU_CC_GX_VSENSE_CLK 18 -#define GPU_CC_SLEEP_CLK 19 +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_AHB_CLK 2 +#define GPU_CC_CX_GFX3D_CLK 3 +#define GPU_CC_CX_GFX3D_SLV_CLK 4 +#define GPU_CC_CX_GMU_CLK 5 +#define GPU_CC_CX_SNOC_DVM_CLK 6 +#define GPU_CC_CXO_AON_CLK 7 +#define GPU_CC_CXO_CLK 8 +#define GPU_CC_GMU_CLK_SRC 9 +#define GPU_CC_GX_CXO_CLK 10 +#define GPU_CC_GX_GFX3D_CLK 11 +#define GPU_CC_GX_GFX3D_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_SLEEP_CLK 14 /* GPU_CC power domains */ -#define CX_GDSC 0 -#define GX_GDSC 1 - -/* GPU_CC resets */ -#define GPUCC_GPU_CC_ACD_BCR 0 -#define GPUCC_GPU_CC_CX_BCR 1 -#define GPUCC_GPU_CC_GFX3D_AON_BCR 2 -#define GPUCC_GPU_CC_GMU_BCR 3 -#define GPUCC_GPU_CC_GX_BCR 4 -#define GPUCC_GPU_CC_RBCPR_BCR 5 -#define GPUCC_GPU_CC_XO_BCR 6 +#define CX_GDSC 0 +#define GX_GDSC 1 #endif