From fc571a94aaf181d2c0c2ee8448d113ca6ee825c7 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 26 Jun 2020 12:46:53 +0530 Subject: [PATCH] disp: msm: dsi: Update pll delay calculation as per latest DSI HPG As per DSI HPG, pll delay should be 25usec for phy ver 4.0 and 100usec for phy ver 2.0 and 3.0. This change updates pll delay calculation during dynamic DSI clock switch accordingly. Change-Id: Ief5cbdc9304cf5ad025fe3bbe689b93834a1f710 Signed-off-by: Ritesh Kumar --- msm/dsi/dsi_display.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/msm/dsi/dsi_display.c b/msm/dsi/dsi_display.c index d0a8418c0360..34ba47b6e59c 100644 --- a/msm/dsi/dsi_display.c +++ b/msm/dsi/dsi_display.c @@ -4326,6 +4326,7 @@ static void _dsi_display_calc_pipe_delay(struct dsi_display *display, struct dsi_display_ctrl *m_ctrl; struct dsi_ctrl *dsi_ctrl; struct dsi_phy_cfg *cfg; + int phy_ver; m_ctrl = &display->ctrl[display->clk_master_idx]; dsi_ctrl = m_ctrl->ctrl; @@ -4363,8 +4364,17 @@ static void _dsi_display_calc_pipe_delay(struct dsi_display *display, ((cfg->timing.lane_v3[4] >> 1) + 1)) / hr_bit_to_esc_ratio); - /* 130 us pll delay recommended by h/w doc */ - delay->pll_delay = ((130 * esc_clk_rate_hz) / 1000000) * 2; + /* + * 100us pll delay recommended for phy ver 2.0 and 3.0 + * 25us pll delay recommended for phy ver 4.0 + */ + phy_ver = dsi_phy_get_version(m_ctrl->phy); + if (phy_ver <= DSI_PHY_VERSION_3_0) + delay->pll_delay = 100; + else + delay->pll_delay = 25; + + delay->pll_delay = ((delay->pll_delay * esc_clk_rate_hz) / 1000000); } static int _dsi_display_dyn_update_clks(struct dsi_display *display,