diff --git a/drivers/gpu/msm/adreno-gpulist.h b/drivers/gpu/msm/adreno-gpulist.h
index 949bcfeee0e9..f7c3563a10c1 100644
--- a/drivers/gpu/msm/adreno-gpulist.h
+++ b/drivers/gpu/msm/adreno-gpulist.h
@@ -789,7 +789,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a630v2 = {
 		.snapshot_size = SZ_1M,
 	},
 	.prim_fifo_threshold = 0x0018000,
-	.pdc_address_offset = 0x00030080,
 	.gmu_major = 1,
 	.gmu_minor = 3,
 	.sqefw_name = "a630_sqe.fw",
@@ -889,7 +888,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a615 = {
 		.snapshot_size = 600 * SZ_1K,
 	},
 	.prim_fifo_threshold = 0x0018000,
-	.pdc_address_offset = 0x00030080,
 	.gmu_major = 1,
 	.gmu_minor = 3,
 	.sqefw_name = "a630_sqe.fw",
@@ -917,7 +915,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a618 = {
 		.snapshot_size = SZ_1M,
 	},
 	.prim_fifo_threshold = 0x0018000,
-	.pdc_address_offset = 0x00030090,
 	.gmu_major = 1,
 	.gmu_minor = 7,
 	.sqefw_name = "a630_sqe.fw",
@@ -1046,7 +1043,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a620 = {
 		.snapshot_size = 2 * SZ_1M,
 	},
 	.prim_fifo_threshold = 0x0010000,
-	.pdc_address_offset = 0x000300a0,
 	.gmu_major = 2,
 	.gmu_minor = 0,
 	.sqefw_name = "a650_sqe.fw",
@@ -1137,7 +1133,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a640 = {
 		.snapshot_size = 2 * SZ_1M,
 	},
 	.prim_fifo_threshold = 0x00200000,
-	.pdc_address_offset = 0x00030090,
 	.gmu_major = 2,
 	.gmu_minor = 0,
 	.sqefw_name = "a630_sqe.fw",
@@ -1218,7 +1213,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650 = {
 		.snapshot_size = 2 * SZ_1M,
 	},
 	.prim_fifo_threshold = 0x00300000,
-	.pdc_address_offset = 0x000300A0,
 	.gmu_major = 2,
 	.gmu_minor = 0,
 	.sqefw_name = "a650_sqe.fw",
@@ -1248,7 +1242,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a650v2 = {
 		.snapshot_size = 2 * SZ_1M,
 	},
 	.prim_fifo_threshold = 0x00300000,
-	.pdc_address_offset = 0x000300A0,
 	.gmu_major = 2,
 	.gmu_minor = 0,
 	.sqefw_name = "a650_sqe.fw",
@@ -1275,7 +1268,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a680 = {
 		.snapshot_size = SZ_1M,
 	},
 	.prim_fifo_threshold = 0x00400000,
-	.pdc_address_offset = 0x00030090,
 	.gmu_major = 2,
 	.gmu_minor = 0,
 	.sqefw_name = "a630_sqe.fw",
@@ -1353,7 +1345,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = {
 		.snapshot_size = SZ_1M,
 	},
 	.prim_fifo_threshold = 0x00080000,
-	.pdc_address_offset = 0x00030080,
 	.sqefw_name = "a630_sqe.fw",
 	.gmufw_name = "a612_rgmu.bin",
 	.zap_name = "a612_zap",
@@ -1379,7 +1370,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a616 = {
 		.snapshot_size = SZ_1M,
 	},
 	.prim_fifo_threshold = 0x0018000,
-	.pdc_address_offset = 0x00030080,
 	.gmu_major = 1,
 	.gmu_minor = 3,
 	.sqefw_name = "a630_sqe.fw",
@@ -1520,7 +1510,6 @@ static const struct adreno_a6xx_core adreno_gpu_core_a660 = {
 		.snapshot_size = SZ_1M,
 	},
 	.prim_fifo_threshold = 0x00300000,
-	.pdc_address_offset = 0x0,
 	.gmu_major = 2,
 	.gmu_minor = 0,
 	.sqefw_name = "a660_sqe.fw",
diff --git a/drivers/gpu/msm/adreno_a6xx.h b/drivers/gpu/msm/adreno_a6xx.h
index b2316692b341..09b55fa184e3 100644
--- a/drivers/gpu/msm/adreno_a6xx.h
+++ b/drivers/gpu/msm/adreno_a6xx.h
@@ -42,8 +42,6 @@ struct adreno_a6xx_core {
 	u32 gmu_minor;
 	/** @prim_fifo_threshold: target specific value for PC_DBG_ECO_CNTL */
 	unsigned int prim_fifo_threshold;
-	/** @pdc_address_offset: Offset for the PDC region for the target */
-	unsigned int pdc_address_offset;
 	/** @sqefw_name: Name of the SQE microcode file */
 	const char *sqefw_name;
 	/** @gmufw_name: Name of the GMU firmware file */
diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c
index 5825a90b80a6..5d0c82de101e 100644
--- a/drivers/gpu/msm/adreno_a6xx_gmu.c
+++ b/drivers/gpu/msm/adreno_a6xx_gmu.c
@@ -120,6 +120,13 @@ static int a6xx_load_pdc_ucode(struct kgsl_device *device)
 	void __iomem *cfg = NULL, *seq = NULL;
 	const struct adreno_a6xx_core *a6xx_core = to_a6xx_core(adreno_dev);
 	u32 vrm_resource_addr = cmd_db_read_addr("vrm.soc");
+	u32 xo_resource_addr = cmd_db_read_addr("xo.lvl");
+
+	if (!xo_resource_addr) {
+		dev_err(&gmu->pdev->dev,
+				"Failed to get 'xo.lvl' addr from cmd_db\n");
+		return -ENOENT;
+	}
 
 	/*
 	 * Older A6x platforms specified PDC registers in the DT using a
@@ -206,7 +213,7 @@ static int a6xx_load_pdc_ucode(struct kgsl_device *device)
 	_regwrite(cfg, PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);
 
 	_regwrite(cfg, PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2,
-			a6xx_core->pdc_address_offset);
+			xo_resource_addr);
 
 	_regwrite(cfg, PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x0);
 
@@ -236,7 +243,7 @@ static int a6xx_load_pdc_ucode(struct kgsl_device *device)
 	_regwrite(cfg, PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108);
 
 	_regwrite(cfg, PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET * 2,
-			a6xx_core->pdc_address_offset);
+			xo_resource_addr);
 
 	_regwrite(cfg, PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x3);