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Merge tag 'drm-intel-next-2016-08-08' of git://anongit.freedesktop.org/drm-intel into drm-next
- refactor ddi buffer programming a bit (Ville) - large-scale renaming to untangle naming in the gem code (Chris) - rework vma/active tracking for accurately reaping idle mappings of shared objects (Chris) - misc dp sst/mst probing corner case fixes (Ville) - tons of cleanup&tunings all around in gem - lockless (rcu-protected) request lookup, plus use it everywhere for non(b)locking waits (Chris) - pipe crc debugfs fixes (Rodrigo) - random fixes all over * tag 'drm-intel-next-2016-08-08' of git://anongit.freedesktop.org/drm-intel: (222 commits) drm/i915: Update DRIVER_DATE to 20160808 drm/i915: fix aliasing_ppgtt leak drm/i915: Update comment before i915_spin_request drm/i915: Use drm official vblank_no_hw_counter callback. drm/i915: Fix copy_to_user usage for pipe_crc Revert "drm/i915: Track active streams also for DP SST" drm/i915: fix WaInsertDummyPushConstPs drm/i915: Assert that the request hasn't been retired drm/i915: Repack fence tiling mode and stride into a single integer drm/i915: Document and reject invalid tiling modes drm/i915: Remove locking for get_tiling drm/i915: Remove pinned check from madvise ioctl drm/i915: Reduce locking inside swfinish ioctl drm/i915: Remove (struct_mutex) locking for busy-ioctl drm/i915: Remove (struct_mutex) locking for wait-ioctl drm/i915: Do a nonblocking wait first in pread/pwrite drm/i915: Remove unused no-shrinker-steal drm/i915: Tidy generation of the GTT mmap offset drm/i915/shrinker: Wait before acquiring struct_mutex under oom drm/i915: Simplify do_idling() (Ironlake vt-d w/a) ...
This commit is contained in:
commit
fc93ff608b
62 changed files with 6280 additions and 5999 deletions
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@ -62,6 +62,30 @@ extern "C" {
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#define I915_ERROR_UEVENT "ERROR"
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#define I915_RESET_UEVENT "RESET"
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/*
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* MOCS indexes used for GPU surfaces, defining the cacheability of the
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* surface data and the coherency for this data wrt. CPU vs. GPU accesses.
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*/
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enum i915_mocs_table_index {
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/*
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* Not cached anywhere, coherency between CPU and GPU accesses is
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* guaranteed.
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*/
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I915_MOCS_UNCACHED,
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/*
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* Cacheability and coherency controlled by the kernel automatically
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* based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
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* usage of the surface (used for display scanout or not).
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*/
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I915_MOCS_PTE,
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/*
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* Cached in all GPU caches available on the platform.
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* Coherency between CPU and GPU accesses to the surface is not
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* guaranteed without extra synchronization.
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*/
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I915_MOCS_CACHED,
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};
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/* Each region is a minimum of 16k, and there are at most 255 of them.
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*/
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#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
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@ -698,15 +722,20 @@ struct drm_i915_gem_exec_object2 {
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*/
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__u64 offset;
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#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
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#define EXEC_OBJECT_NEEDS_GTT (1<<1)
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#define EXEC_OBJECT_WRITE (1<<2)
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#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
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#define EXEC_OBJECT_NEEDS_GTT (1<<1)
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#define EXEC_OBJECT_WRITE (1<<2)
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#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
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#define EXEC_OBJECT_PINNED (1<<4)
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#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1)
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#define EXEC_OBJECT_PINNED (1<<4)
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#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
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/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
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#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PAD_TO_SIZE<<1)
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__u64 flags;
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__u64 rsvd1;
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union {
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__u64 rsvd1;
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__u64 pad_to_size;
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};
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__u64 rsvd2;
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};
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@ -897,6 +926,7 @@ struct drm_i915_gem_caching {
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#define I915_TILING_NONE 0
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#define I915_TILING_X 1
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#define I915_TILING_Y 2
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#define I915_TILING_LAST I915_TILING_Y
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#define I915_BIT_6_SWIZZLE_NONE 0
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#define I915_BIT_6_SWIZZLE_9 1
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