From fd141c239846197b65c36bed66fa106608cc4df1 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 8 Jul 2021 09:12:22 +0530 Subject: [PATCH] clk: qcom: clk-alpha-pll: Update the steps to slew the Lucid PLL When PLL HW_UPDATE_LOGIC_BYPASS bit is not set then PLL can be updated dynamically by setting the PLL_UPDATE bit in mode register and hardware would clear the PLL_UPDATE automatically when PLL_ACK_LATCH is asserted. Change-Id: I1c568c9fdd37a554d71fc5c3d840a71e983baf60 Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index e40f344609f8..391761765f3b 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -2895,7 +2895,12 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate, /* Wait for 2 reference cycles before checking the ACK bit. */ udelay(1); regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val); - if (!(regval & ALPHA_PLL_ACK_LATCH)) { + if (!(regval & PLL_UPDATE_BYPASS)) { + ret = wait_for_pll_update(pll); + if (ret) + WARN_CLK(&pll->clkr.hw, 1, "PLL Update clear failed\n"); + return ret; + } else if (!(regval & ALPHA_PLL_ACK_LATCH)) { WARN_CLK(&pll->clkr.hw, 1, "PLL latch failed. Output may be unstable!\n"); return -EINVAL;