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cnss2: Add code to fallback to non-contiguous FW mem allocation
Add code to fallback to non-contiguous FW mem allocation on failure to allocate contiguous memory. Change-Id: Idbc7ff7f9ea4d2157e3b549dde8ee090a0f0b412 Signed-off-by: Mohammed Siddiq <quic_msiddiq@quicinc.com>
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2 changed files with 36 additions and 14 deletions
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@ -1,5 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */
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/* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/cma.h>
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#include <linux/firmware.h>
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@ -3984,15 +3986,27 @@ int cnss_pci_alloc_fw_mem(struct cnss_pci_data *pci_priv)
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for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
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if (!fw_mem[i].va && fw_mem[i].size) {
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retry:
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fw_mem[i].va =
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dma_alloc_attrs(dev, fw_mem[i].size,
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&fw_mem[i].pa, GFP_KERNEL,
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fw_mem[i].attrs);
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if (!fw_mem[i].va) {
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if ((fw_mem[i].attrs &
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DMA_ATTR_FORCE_CONTIGUOUS)) {
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fw_mem[i].attrs &=
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~DMA_ATTR_FORCE_CONTIGUOUS;
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cnss_pr_dbg("Fallback to non-contiguous memory for FW, Mem type: %u\n",
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fw_mem[i].type);
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goto retry;
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}
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cnss_pr_err("Failed to allocate memory for FW, size: 0x%zx, type: %u\n",
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fw_mem[i].size, fw_mem[i].type);
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BUG();
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CNSS_ASSERT(0);
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return -ENOMEM;
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}
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}
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}
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@ -5083,17 +5097,21 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic)
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mhi_dump_sfr(pci_priv->mhi_ctrl);
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cnss_pr_dbg("Collect remote heap dump segment\n");
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for (i = 0, j = 0; i < plat_priv->fw_mem_seg_len; i++) {
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if (fw_mem[i].type == CNSS_MEM_TYPE_DDR) {
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cnss_pci_add_dump_seg(pci_priv, dump_seg,
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CNSS_FW_REMOTE_HEAP, j,
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fw_mem[i].va, fw_mem[i].pa,
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fw_mem[i].size);
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dump_seg++;
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dump_data->nentries++;
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j++;
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if (fw_mem[i].attrs & DMA_ATTR_FORCE_CONTIGUOUS) {
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cnss_pr_dbg("Collect remote heap dump segment\n");
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cnss_pci_add_dump_seg(pci_priv, dump_seg,
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CNSS_FW_REMOTE_HEAP, j,
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fw_mem[i].va,
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fw_mem[i].pa,
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fw_mem[i].size);
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dump_seg++;
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dump_data->nentries++;
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j++;
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} else {
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cnss_pr_dbg("Skip remote heap dumps as it is non-contiguous\n");
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}
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}
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}
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@ -5138,7 +5156,8 @@ void cnss_pci_clear_dump_info(struct cnss_pci_data *pci_priv)
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}
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for (i = 0, j = 0; i < plat_priv->fw_mem_seg_len; i++) {
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if (fw_mem[i].type == CNSS_MEM_TYPE_DDR) {
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if (fw_mem[i].type == CNSS_MEM_TYPE_DDR &&
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(fw_mem[i].attrs & DMA_ATTR_FORCE_CONTIGUOUS)) {
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cnss_pci_remove_dump_seg(pci_priv, dump_seg,
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CNSS_FW_REMOTE_HEAP, j,
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fw_mem[i].va, fw_mem[i].pa,
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@ -1,5 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */
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/* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/firmware.h>
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#include <linux/module.h>
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@ -2206,7 +2208,8 @@ static void cnss_wlfw_request_mem_ind_cb(struct qmi_handle *qmi_wlfw,
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ind_msg->mem_seg[i].size, ind_msg->mem_seg[i].type);
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plat_priv->fw_mem[i].type = ind_msg->mem_seg[i].type;
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plat_priv->fw_mem[i].size = ind_msg->mem_seg[i].size;
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if (plat_priv->fw_mem[i].type == CNSS_MEM_TYPE_DDR)
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if (!plat_priv->fw_mem[i].va &&
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plat_priv->fw_mem[i].type == CNSS_MEM_TYPE_DDR)
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plat_priv->fw_mem[i].attrs |=
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DMA_ATTR_FORCE_CONTIGUOUS;
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}
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