From 478799800f64151a6f866e20da712eebbb71fdb6 Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Thu, 5 Nov 2020 15:01:53 -0800 Subject: [PATCH 1/2] dt-bindings: Document the qcom,power-always-on property for SMMU devices Document the qcom,power-always-on property for SMMU devices. This property specifies that the votes for power resources for an SMMU should always be maintained. Change-Id: I854e07b65d93ed78f9d3e270149d28ef6b599039 --- bindings/iommu/arm,smmu.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bindings/iommu/arm,smmu.txt b/bindings/iommu/arm,smmu.txt index 9e3e515e4e96..29e79cddee88 100644 --- a/bindings/iommu/arm,smmu.txt +++ b/bindings/iommu/arm,smmu.txt @@ -182,6 +182,13 @@ conditions. that interconnect votes will be maintained irrespective of the CPUSS' state (awake or asleep). +- qcom,power-always-on: + Boolean property which indicates that votes for power + resources (i.e. regulators, clocks, buses) should + always be maintained. This is required when the latency + for the SMMU's operation is greatly increased by adding and + removing votes for power resources. + ** Deprecated properties: - mmu-masters (deprecated in favour of the generic "iommus" binding) : From 573cab957be2a46a86f112117364e47cad59d0b5 Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Thu, 5 Nov 2020 15:05:28 -0800 Subject: [PATCH 2/2] ARM: dts: msm: Enable qcom,power-always-on for GPU SMMUs on GKI targets The IOMMU page table management code is not optimal from a performance perspective in the GKI configuration, relative to the downstream implementation. When the GPU enters slumber, and requests the SMMU driver to unmap memory from the stage 1 page tables of the GPU. When unmapping memory, the SMMU driver must access the GPU SMMU's register space, so it must vote for power resources to access the TLB invalidation registers. When the GPU is in slumber, there aren't votes for the GPU SMMU's power resources, so the SMMU driver constantly ends up enabling/disabling the power resources, which takes a considerable amount of time. When paired with the suboptimal IOMMU page table management code, this leads to performance issues where the time taken to unmap memory is large. Thus, for all targets that support GKI, add the qcom,power-always-on property for the GPU SMMUs of these targets, to remove the latency incurred by having to enable/disable power resources in the GKI configuration. Change-Id: Id3237214e44c008871d01ec6652b08c4fb24e41c --- qcom/msm-arm-smmu-holi.dtsi | 1 + qcom/msm-arm-smmu-lahaina.dtsi | 1 + qcom/msm-arm-smmu-shima.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/qcom/msm-arm-smmu-holi.dtsi b/qcom/msm-arm-smmu-holi.dtsi index 20343e67832b..0b7fb0427195 100644 --- a/qcom/msm-arm-smmu-holi.dtsi +++ b/qcom/msm-arm-smmu-holi.dtsi @@ -7,6 +7,7 @@ #iommu-cells = <1>; qcom,use-3-lvl-tables; #global-interrupts = <2>; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>; clock-names = "gcc_gpu_memnoc_gfx_clk"; diff --git a/qcom/msm-arm-smmu-lahaina.dtsi b/qcom/msm-arm-smmu-lahaina.dtsi index de6054d5d612..f373834017d1 100644 --- a/qcom/msm-arm-smmu-lahaina.dtsi +++ b/qcom/msm-arm-smmu-lahaina.dtsi @@ -15,6 +15,7 @@ #address-cells = <1>; ranges; dma-coherent; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cc_cx_gdsc>; diff --git a/qcom/msm-arm-smmu-shima.dtsi b/qcom/msm-arm-smmu-shima.dtsi index c9c71235d746..4867686e4486 100644 --- a/qcom/msm-arm-smmu-shima.dtsi +++ b/qcom/msm-arm-smmu-shima.dtsi @@ -15,6 +15,7 @@ #address-cells = <1>; ranges; dma-coherent; + qcom,power-always-on; qcom,regulator-names = "vdd"; vdd-supply = <&gpu_cx_gdsc>;