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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-10 22:40:54 -04:00
bindings: Documentation: update DisplayPort node
Update the documentation for the DisplayPort node on Lahaina. Change-Id: I22e8751db2f9b47fbdc433a2687aee41e4e746af
This commit is contained in:
Tatenda Chipeperekwa
Gerrit - the friendly Code Review server
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902734d2dc
commit
fde81ee3b1
1 changed files with 143 additions and 115 deletions
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@ -4,28 +4,30 @@ DP Controller: Required properties:
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- compatible: Should be "qcom,dp-display".
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- reg: Base address and length of DP hardware's memory mapped regions.
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- reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region.
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"dp_phy" - DP PHY memory region.
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"dp_ahb" - AHB memory region.
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"dp_aux" - AUX memory region.
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"dp_link" - LINK memory region.
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"dp_p0" - PCLK0 memory region.
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"dp_phy" - PHY memory region.
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"dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region.
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"dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region.
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"dp_mmss_cc" - Display Clock Control memory region.
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"qfprom_physical" - QFPROM Phys memory region.
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"dp_pll" - USB3 DP combo PLL memory region.
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"usb3_dp_com" - USB3 DP PHY combo memory region.
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"hdcp_physical" - DP HDCP memory region.
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"dp_p1" - DP PCLK1 memory region.
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"gdsc" - DISPCC GDSC memory region.
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- cell-index: Specifies the controller instance.
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- #clock-cells: Denotes the DP driver as a clock producer (has one or more clock outputs)
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- clocks: Clocks required for Display Port operation.
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- clock-names: Names of the clocks corresponding to handles. Following clocks are required:
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"core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk",
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"core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk",
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"ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent".
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- gdsc-supply: phandle to gdsc regulator node.
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"core_aux_clk", "core_usb_ref_clk_src", "core_usb_pipe_clk", "link_clk",
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"link_iface_clk", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg",
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"strm0_pixel_clk", "strm1_pixel_clk".
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- vdda-1p2-supply: phandle to vdda 1.2V regulator node.
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- vdda-0p9-supply: phandle to vdda 0.9V regulator node.
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- interrupt-parent phandle to the interrupt parent device node.
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- interrupts: The interrupt signal from the DSI block.
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- qcom,aux-en-gpio: Specifies the aux-channel enable gpio.
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- qcom,aux-sel-gpio: Specifies the aux-channel select gpio.
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- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio.
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- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first
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entry in this array corresponds to the register offset
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within DP AUX, while the remaining entries indicate the
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@ -72,12 +74,14 @@ DP Controller: Required properties:
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- qcom,fec-feature-enable: FEC feature enable control node.
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- qcom,max-dp-dsc-blks: An integer specifying the max. DSC blocks available for Display port.
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- qcom,max-dp-dsc-input-width-pixs: An integer specifying the max. input width of pixels for each DSC block.
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- qcom,dp-usbpd-detection: Phandle for the PMI regulator node for USB PHY PD detection.
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- qcom,altmode-dev: Phandle for the AltMode GLink driver.
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- usb-controller: Phandle for the USB controller.
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- qcom,pll-revision: PLL hardware revision.
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- qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation.
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- qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch.
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- qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support.
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- qcom,<type>-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DSI module. The module "types"
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can be "core", "ctrl", and "phy". Within the same type,
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- qcom,<type>-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DP module. The module "types"
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can be "core", "ctrl", "pll" and "phy". Within the same type,
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there can be more than one instance of this binding,
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in which case the entry would be appended with the
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supply entry index.
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@ -96,6 +100,10 @@ msm_ext_disp is a device which manages the interaction between external
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display interfaces, e.g. Display Port, and the audio subsystem.
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Optional properties:
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- vdd_mx-supply: phandle to vdda MX regulator node
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- qcom,aux-en-gpio: Specifies the aux-channel enable gpio.
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- qcom,aux-sel-gpio: Specifies the aux-channel select gpio.
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- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio.
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- qcom,ext-disp: phandle for msm-ext-display module
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- compatible: Must be "qcom,msm-ext-disp"
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- qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node
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@ -117,121 +125,141 @@ these devices will be disabled as well. Ex. Audio Codec device.
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- compatible : "qcom,msm-ext-disp-audio-codec-rx";
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Example:
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ext_disp: qcom,msm-ext-disp {
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compatible = "qcom,msm-ext-disp";
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ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
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compatible = "qcom,msm-ext-disp-audio-codec-rx";
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};
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ext_disp: qcom,msm-ext-disp {
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compatible = "qcom,msm-ext-disp";
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ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
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compatible = "qcom,msm-ext-disp-audio-codec-rx";
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};
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};
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sde_dp: qcom,dp_display@0{
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cell-index = <0>;
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compatible = "qcom,dp-display";
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sde_dp: qcom,dp_display@0 {
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cell-index = <0>;
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compatible = "qcom,dp-display";
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gdsc-supply = <&mdss_core_gdsc>;
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vdda-1p2-supply = <&pm8998_l26>;
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vdda-0p9-supply = <&pm8998_l1>;
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qcom,dp-aux-switch = <&fsa4480>;
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qcom,ext-disp = <&ext_disp>;
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qcom,altmode-dev = <&altmode 0>;
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usb-controller = <&usb0>;
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reg = <0xae90000 0xa84>,
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reg = <0xae90000 0x0dc>,
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<0xae90200 0x0c0>,
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<0xae90400 0x508>,
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<0xae91000 0x094>,
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<0x88eaa00 0x200>,
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<0x88ea200 0x200>,
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<0x88ea600 0x200>,
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<0xaf02000 0x1a0>,
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<0x780000 0x621c>,
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<0x88ea030 0x10>,
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<0x88e8000 0x621c>,
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<0x0aee1000 0x034>;
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reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
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"dp_mmss_cc", "qfprom_physical", "dp_pll",
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"usb3_dp_com", "hdcp_physical";
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<0x88ea000 0x200>,
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<0x88e8000 0x20>,
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<0x0aee1000 0x034>,
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<0xae91400 0x094>,
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<0xaf03000 0x8>;
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reg-names = "dp_ahb", "dp_aux", "dp_link",
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"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
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"dp_mmss_cc", "dp_pll", "usb3_dp_com",
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"hdcp_physical", "dp_p1", "gdsc";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <12 0>;
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interrupt-parent = <&mdss_mdp>;
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interrupts = <12 0>;
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clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
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<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
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<&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
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clock-names = "core_aux_clk", "core_usb_ref_clk_src",
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"core_usb_ref_clk", "core_usb_cfg_ahb_clk",
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"core_usb_pipe_clk", "ctrl_link_clk",
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"ctrl_link_iface_clk", "ctrl_crypto_clk",
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"ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent";
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#clock-cells = <1>;
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clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
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<&sde_dp DP_PHY_PLL_VCO_DIV_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
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clock-names = "core_aux_clk", "core_usb_ref_clk_src",
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"core_usb_pipe_clk", "link_clk", "link_iface_clk",
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"pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg",
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"strm0_pixel_clk", "strm1_pixel_clk";
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qcom,dp-usbpd-detection = <&pm8150b_pdphy>;
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qcom,ext-disp = <&ext_disp>;
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qcom,phy-version = <0x420>;
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qcom,dp-aux-switch = <&fsa4480>;
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qcom,pll-revision = "5nm-v1";
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qcom,phy-version = <0x420>;
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qcom,dp-aux-switch = <&fsa4480>;
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qcom,aux-cfg0-settings = [1c 00];
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qcom,aux-cfg1-settings = [20 13 23 1d];
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qcom,aux-cfg2-settings = [24 00];
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qcom,aux-cfg3-settings = [28 00];
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qcom,aux-cfg4-settings = [2c 0a];
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qcom,aux-cfg5-settings = [30 26];
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qcom,aux-cfg6-settings = [34 0a];
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qcom,aux-cfg7-settings = [38 03];
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qcom,aux-cfg8-settings = [3c bb];
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qcom,aux-cfg9-settings = [40 03];
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qcom,max-pclk-frequency-khz = <593470>;
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qcom,mst-enable;
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qcom,dsc-feature-enable;
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qcom,fec-feature-enable;
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qcom,max-dp-dsc-blks = <2>;
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qcom,max-dp-dsc-input-width-pixs = <2048>;
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pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
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pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;
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pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;
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qcom,aux-en-gpio = <&tlmm 43 0>;
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qcom,aux-sel-gpio = <&tlmm 51 0>;
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qcom,usbplug-cc-gpio = <&tlmm 38 0>;
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qcom,core-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,aux-cfg0-settings = [1c 00];
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qcom,aux-cfg1-settings = [20 13 23 1d];
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qcom,aux-cfg2-settings = [24 00];
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qcom,aux-cfg3-settings = [28 00];
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qcom,aux-cfg4-settings = [2c 0a];
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qcom,aux-cfg5-settings = [30 26];
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qcom,aux-cfg6-settings = [34 0a];
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qcom,aux-cfg7-settings = [38 03];
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qcom,aux-cfg8-settings = [3c bb];
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qcom,aux-cfg9-settings = [40 03];
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qcom,max-pclk-frequency-khz = <593470>;
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qcom,mst-enable;
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qcom,dsc-feature-enable;
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qcom,fec-feature-enable;
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qcom,max-dp-dsc-blks = <2>;
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qcom,max-dp-dsc-input-width-pixs = <2048>;
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qcom,core-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "gdsc";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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vdda-1p2-supply = <&L6B>;
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vdda-0p9-supply = <&L1B>;
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vdd_mx-supply = <&VDD_MXA_LEVEL>;
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1200000>;
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qcom,supply-enable-load = <21700>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,phy-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1200000>;
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qcom,supply-enable-load = <21800>;
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qcom,supply-disable-load = <4>;
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};
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qcom,phy-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-0p9";
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qcom,supply-min-voltage = <912000>;
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qcom,supply-max-voltage = <912000>;
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qcom,supply-enable-load = <115000>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,phy-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,core-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,phy-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-0p9";
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qcom,supply-min-voltage = <880000>;
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qcom,supply-max-voltage = <880000>;
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qcom,supply-enable-load = <36000>;
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qcom,supply-disable-load = <32>;
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};
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qcom,core-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "refgen";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,pll-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,pll-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdd_mx";
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qcom,supply-min-voltage =
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<RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,supply-max-voltage =
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<RPMH_REGULATOR_LEVEL_MAX>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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