mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-29 19:21:31 -04:00
ARM: SoC driver updates for 4.16
A number of new drivers get added this time, along with many low-priority
bugfixes. The most interesting changes by subsystem are:
bus drivers:
- Updates to the Broadcom bus interface driver to support newer SoC types
- The TI OMAP sysc driver now supports updated DT bindings
memory controllers:
- A new driver for Tegra186 gets added
- A new driver for the ti-emif sram, to allow relocating
suspend/resume handlers there
SoC specific:
- A new driver for Qualcomm QMI, the interface to the modem on MSM SoCs
- A new driver for power domains on the actions S700 SoC
- A driver for the Xilinx Zynq VCU logicoreIP
reset controllers:
- A new driver for Amlogic Meson-AGX
- various bug fixes
tee subsystem:
- A new user interface got added to enable asynchronous communication
with the TEE supplicant.
- A new method of using user space memory for communication with
the TEE is added
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver updates from Arnd Bergmann:
"A number of new drivers get added this time, along with many
low-priority bugfixes. The most interesting changes by subsystem are:
bus drivers:
- Updates to the Broadcom bus interface driver to support newer SoC
types
- The TI OMAP sysc driver now supports updated DT bindings
memory controllers:
- A new driver for Tegra186 gets added
- A new driver for the ti-emif sram, to allow relocating
suspend/resume handlers there
SoC specific:
- A new driver for Qualcomm QMI, the interface to the modem on MSM
SoCs
- A new driver for power domains on the actions S700 SoC
- A driver for the Xilinx Zynq VCU logicoreIP
reset controllers:
- A new driver for Amlogic Meson-AGX
- various bug fixes
tee subsystem:
- A new user interface got added to enable asynchronous communication
with the TEE supplicant.
- A new method of using user space memory for communication with the
TEE is added"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (84 commits)
of: platform: fix OF node refcount leak
soc: fsl: guts: Add a NULL check for devm_kasprintf()
bus: ti-sysc: Fix smartreflex sysc mask
psci: add CPU_IDLE dependency
soc: xilinx: Fix Kconfig alignment
soc: xilinx: xlnx_vcu: Use bitwise & rather than logical && on clkoutdiv
soc: xilinx: xlnx_vcu: Depends on HAS_IOMEM for xlnx_vcu
soc: bcm: brcmstb: Be multi-platform compatible
soc: brcmstb: biuctrl: exit without warning on non brcmstb platforms
Revert "soc: brcmstb: Only register SoC device on STB platforms"
bus: omap: add MODULE_LICENSE tags
soc: brcmstb: Only register SoC device on STB platforms
tee: shm: Potential NULL dereference calling tee_shm_register()
soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver
soc: xilinx: Create folder structure for soc specific drivers
of: platform: populate /firmware/ node from of_platform_default_populate_init()
soc: samsung: Add SPDX license identifiers
soc: qcom: smp2p: Use common error handling code in qcom_smp2p_probe()
tee: shm: don't put_page on null shm->pages
...
This commit is contained in:
Linus Torvalds
commit
fe53d1443a
93 changed files with 6909 additions and 735 deletions
|
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@ -375,3 +375,8 @@ static void __exit omap_l3_exit(void)
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platform_driver_unregister(&omap_l3_driver);
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}
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module_exit(omap_l3_exit);
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MODULE_AUTHOR("Santosh Shilimkar");
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MODULE_AUTHOR("Sricharan R");
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MODULE_DESCRIPTION("OMAP L3 Interconnect error handling driver");
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MODULE_LICENSE("GPL v2");
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@ -309,3 +309,9 @@ static void __exit omap3_l3_exit(void)
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platform_driver_unregister(&omap3_l3_driver);
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}
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module_exit(omap3_l3_exit);
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MODULE_AUTHOR("Felipe Balbi");
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MODULE_AUTHOR("Santosh Shilimkar");
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MODULE_AUTHOR("Sricharan R");
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MODULE_DESCRIPTION("OMAP3XXX L3 Interconnect Driver");
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MODULE_LICENSE("GPL");
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@ -18,6 +18,9 @@
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#include <linux/pm_runtime.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_data/ti-sysc.h>
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#include <dt-bindings/bus/ti-sysc.h>
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enum sysc_registers {
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SYSC_REVISION,
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@ -36,6 +39,9 @@ enum sysc_clocks {
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static const char * const clock_names[] = { "fck", "ick", };
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#define SYSC_IDLEMODE_MASK 3
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#define SYSC_CLOCKACTIVITY_MASK 3
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/**
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* struct sysc - TI sysc interconnect target module registers and capabilities
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* @dev: struct device pointer
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@ -45,6 +51,10 @@ static const char * const clock_names[] = { "fck", "ick", };
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* @offsets: register offsets from module base
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* @clocks: clocks used by the interconnect target module
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* @legacy_mode: configured for legacy mode if set
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* @cap: interconnect target module capabilities
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* @cfg: interconnect target module configuration
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* @name: name if available
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* @revision: interconnect target module revision
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*/
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struct sysc {
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struct device *dev;
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@ -54,12 +64,34 @@ struct sysc {
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int offsets[SYSC_MAX_REGS];
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struct clk *clocks[SYSC_MAX_CLOCKS];
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const char *legacy_mode;
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const struct sysc_capabilities *cap;
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struct sysc_config cfg;
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const char *name;
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u32 revision;
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};
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static u32 sysc_read(struct sysc *ddata, int offset)
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{
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if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
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u32 val;
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val = readw_relaxed(ddata->module_va + offset);
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val |= (readw_relaxed(ddata->module_va + offset + 4) << 16);
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return val;
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}
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return readl_relaxed(ddata->module_va + offset);
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}
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static u32 sysc_read_revision(struct sysc *ddata)
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{
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return readl_relaxed(ddata->module_va +
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ddata->offsets[SYSC_REVISION]);
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int offset = ddata->offsets[SYSC_REVISION];
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if (offset < 0)
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return 0;
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return sysc_read(ddata, offset);
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}
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static int sysc_get_one_clock(struct sysc *ddata,
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@ -206,6 +238,21 @@ static int sysc_check_children(struct sysc *ddata)
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return 0;
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}
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/*
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* So far only I2C uses 16-bit read access with clockactivity with revision
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* in two registers with stride of 4. We can detect this based on the rev
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* register size to configure things far enough to be able to properly read
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* the revision register.
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*/
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static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
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{
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if (resource_size(res) == 8) {
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dev_dbg(ddata->dev,
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"enabling 16-bit and clockactivity quirks\n");
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ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
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}
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}
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/**
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* sysc_parse_one - parses the interconnect target module registers
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* @ddata: device driver data
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@ -236,6 +283,8 @@ static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
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}
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ddata->offsets[reg] = res->start - ddata->module_pa;
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if (reg == SYSC_REVISION)
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sysc_check_quirk_16bit(ddata, res);
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return 0;
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}
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@ -369,22 +418,12 @@ static int sysc_map_and_check_registers(struct sysc *ddata)
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*/
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static int sysc_show_rev(char *bufp, struct sysc *ddata)
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{
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int error, len;
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int len;
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if (ddata->offsets[SYSC_REVISION] < 0)
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return sprintf(bufp, ":NA");
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error = pm_runtime_get_sync(ddata->dev);
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if (error < 0) {
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pm_runtime_put_noidle(ddata->dev);
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return 0;
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}
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len = sprintf(bufp, ":%08x", sysc_read_revision(ddata));
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pm_runtime_mark_last_busy(ddata->dev);
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pm_runtime_put_autosuspend(ddata->dev);
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len = sprintf(bufp, ":%08x", ddata->revision);
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return len;
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}
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@ -464,6 +503,151 @@ static const struct dev_pm_ops sysc_pm_ops = {
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NULL)
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};
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/* At this point the module is configured enough to read the revision */
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static int sysc_init_module(struct sysc *ddata)
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{
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int error;
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error = pm_runtime_get_sync(ddata->dev);
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if (error < 0) {
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pm_runtime_put_noidle(ddata->dev);
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return 0;
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}
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ddata->revision = sysc_read_revision(ddata);
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pm_runtime_put_sync(ddata->dev);
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return 0;
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}
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static int sysc_init_sysc_mask(struct sysc *ddata)
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{
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struct device_node *np = ddata->dev->of_node;
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int error;
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u32 val;
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error = of_property_read_u32(np, "ti,sysc-mask", &val);
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if (error)
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return 0;
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if (val)
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ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
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else
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ddata->cfg.sysc_val = ddata->cap->sysc_mask;
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return 0;
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}
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static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
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const char *name)
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{
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struct device_node *np = ddata->dev->of_node;
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struct property *prop;
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const __be32 *p;
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u32 val;
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of_property_for_each_u32(np, name, prop, p, val) {
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if (val >= SYSC_NR_IDLEMODES) {
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dev_err(ddata->dev, "invalid idlemode: %i\n", val);
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return -EINVAL;
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}
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*idlemodes |= (1 << val);
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}
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return 0;
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}
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static int sysc_init_idlemodes(struct sysc *ddata)
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{
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int error;
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error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
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"ti,sysc-midle");
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if (error)
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return error;
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error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
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"ti,sysc-sidle");
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if (error)
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return error;
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return 0;
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}
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/*
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* Only some devices on omap4 and later have SYSCONFIG reset done
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* bit. We can detect this if there is no SYSSTATUS at all, or the
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* SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
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* have multiple bits for the child devices like OHCI and EHCI.
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* Depends on SYSC being parsed first.
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*/
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static int sysc_init_syss_mask(struct sysc *ddata)
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{
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struct device_node *np = ddata->dev->of_node;
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int error;
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u32 val;
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error = of_property_read_u32(np, "ti,syss-mask", &val);
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if (error) {
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if ((ddata->cap->type == TI_SYSC_OMAP4 ||
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ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
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(ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
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ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
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return 0;
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}
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if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
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ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
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ddata->cfg.syss_mask = val;
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return 0;
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}
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/* Device tree configured quirks */
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struct sysc_dts_quirk {
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const char *name;
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u32 mask;
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};
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static const struct sysc_dts_quirk sysc_dts_quirks[] = {
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{ .name = "ti,no-idle-on-init",
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.mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
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{ .name = "ti,no-reset-on-init",
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.mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
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};
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static int sysc_init_dts_quirks(struct sysc *ddata)
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{
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struct device_node *np = ddata->dev->of_node;
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const struct property *prop;
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int i, len, error;
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u32 val;
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ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
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for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
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prop = of_get_property(np, sysc_dts_quirks[i].name, &len);
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if (!prop)
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break;
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ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
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}
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error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
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if (!error) {
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if (val > 255) {
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dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
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val);
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}
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ddata->cfg.srst_udelay = (u8)val;
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}
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return 0;
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}
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static void sysc_unprepare(struct sysc *ddata)
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{
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int i;
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|
|
@ -474,9 +658,230 @@ static void sysc_unprepare(struct sysc *ddata)
|
|||
}
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||||
}
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||||
/*
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* Common sysc register bits found on omap2, also known as type1
|
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*/
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static const struct sysc_regbits sysc_regbits_omap2 = {
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.dmadisable_shift = -ENODEV,
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.midle_shift = 12,
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.sidle_shift = 3,
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.clkact_shift = 8,
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.emufree_shift = 5,
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.enwkup_shift = 2,
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.srst_shift = 1,
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.autoidle_shift = 0,
|
||||
};
|
||||
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static const struct sysc_capabilities sysc_omap2 = {
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.type = TI_SYSC_OMAP2,
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.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
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SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
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SYSC_OMAP2_AUTOIDLE,
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.regbits = &sysc_regbits_omap2,
|
||||
};
|
||||
|
||||
/* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
|
||||
static const struct sysc_capabilities sysc_omap2_timer = {
|
||||
.type = TI_SYSC_OMAP2_TIMER,
|
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.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
|
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SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
|
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SYSC_OMAP2_AUTOIDLE,
|
||||
.regbits = &sysc_regbits_omap2,
|
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.mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
|
||||
};
|
||||
|
||||
/*
|
||||
* SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
|
||||
* with different sidle position
|
||||
*/
|
||||
static const struct sysc_regbits sysc_regbits_omap3_sham = {
|
||||
.dmadisable_shift = -ENODEV,
|
||||
.midle_shift = -ENODEV,
|
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.sidle_shift = 4,
|
||||
.clkact_shift = -ENODEV,
|
||||
.enwkup_shift = -ENODEV,
|
||||
.srst_shift = 1,
|
||||
.autoidle_shift = 0,
|
||||
.emufree_shift = -ENODEV,
|
||||
};
|
||||
|
||||
static const struct sysc_capabilities sysc_omap3_sham = {
|
||||
.type = TI_SYSC_OMAP3_SHAM,
|
||||
.sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
|
||||
.regbits = &sysc_regbits_omap3_sham,
|
||||
};
|
||||
|
||||
/*
|
||||
* AES register bits found on omap3 and later, a variant of
|
||||
* sysc_regbits_omap2 with different sidle position
|
||||
*/
|
||||
static const struct sysc_regbits sysc_regbits_omap3_aes = {
|
||||
.dmadisable_shift = -ENODEV,
|
||||
.midle_shift = -ENODEV,
|
||||
.sidle_shift = 6,
|
||||
.clkact_shift = -ENODEV,
|
||||
.enwkup_shift = -ENODEV,
|
||||
.srst_shift = 1,
|
||||
.autoidle_shift = 0,
|
||||
.emufree_shift = -ENODEV,
|
||||
};
|
||||
|
||||
static const struct sysc_capabilities sysc_omap3_aes = {
|
||||
.type = TI_SYSC_OMAP3_AES,
|
||||
.sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
|
||||
.regbits = &sysc_regbits_omap3_aes,
|
||||
};
|
||||
|
||||
/*
|
||||
* Common sysc register bits found on omap4, also known as type2
|
||||
*/
|
||||
static const struct sysc_regbits sysc_regbits_omap4 = {
|
||||
.dmadisable_shift = 16,
|
||||
.midle_shift = 4,
|
||||
.sidle_shift = 2,
|
||||
.clkact_shift = -ENODEV,
|
||||
.enwkup_shift = -ENODEV,
|
||||
.emufree_shift = 1,
|
||||
.srst_shift = 0,
|
||||
.autoidle_shift = -ENODEV,
|
||||
};
|
||||
|
||||
static const struct sysc_capabilities sysc_omap4 = {
|
||||
.type = TI_SYSC_OMAP4,
|
||||
.sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
|
||||
SYSC_OMAP4_SOFTRESET,
|
||||
.regbits = &sysc_regbits_omap4,
|
||||
};
|
||||
|
||||
static const struct sysc_capabilities sysc_omap4_timer = {
|
||||
.type = TI_SYSC_OMAP4_TIMER,
|
||||
.sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
|
||||
SYSC_OMAP4_SOFTRESET,
|
||||
.regbits = &sysc_regbits_omap4,
|
||||
};
|
||||
|
||||
/*
|
||||
* Common sysc register bits found on omap4, also known as type3
|
||||
*/
|
||||
static const struct sysc_regbits sysc_regbits_omap4_simple = {
|
||||
.dmadisable_shift = -ENODEV,
|
||||
.midle_shift = 2,
|
||||
.sidle_shift = 0,
|
||||
.clkact_shift = -ENODEV,
|
||||
.enwkup_shift = -ENODEV,
|
||||
.srst_shift = -ENODEV,
|
||||
.emufree_shift = -ENODEV,
|
||||
.autoidle_shift = -ENODEV,
|
||||
};
|
||||
|
||||
static const struct sysc_capabilities sysc_omap4_simple = {
|
||||
.type = TI_SYSC_OMAP4_SIMPLE,
|
||||
.regbits = &sysc_regbits_omap4_simple,
|
||||
};
|
||||
|
||||
/*
|
||||
* SmartReflex sysc found on omap34xx
|
||||
*/
|
||||
static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
|
||||
.dmadisable_shift = -ENODEV,
|
||||
.midle_shift = -ENODEV,
|
||||
.sidle_shift = -ENODEV,
|
||||
.clkact_shift = 20,
|
||||
.enwkup_shift = -ENODEV,
|
||||
.srst_shift = -ENODEV,
|
||||
.emufree_shift = -ENODEV,
|
||||
.autoidle_shift = -ENODEV,
|
||||
};
|
||||
|
||||
static const struct sysc_capabilities sysc_34xx_sr = {
|
||||
.type = TI_SYSC_OMAP34XX_SR,
|
||||
.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
|
||||
.regbits = &sysc_regbits_omap34xx_sr,
|
||||
.mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED,
|
||||
};
|
||||
|
||||
/*
|
||||
* SmartReflex sysc found on omap36xx and later
|
||||
*/
|
||||
static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
|
||||
.dmadisable_shift = -ENODEV,
|
||||
.midle_shift = -ENODEV,
|
||||
.sidle_shift = 24,
|
||||
.clkact_shift = -ENODEV,
|
||||
.enwkup_shift = 26,
|
||||
.srst_shift = -ENODEV,
|
||||
.emufree_shift = -ENODEV,
|
||||
.autoidle_shift = -ENODEV,
|
||||
};
|
||||
|
||||
static const struct sysc_capabilities sysc_36xx_sr = {
|
||||
.type = TI_SYSC_OMAP36XX_SR,
|
||||
.sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
|
||||
.regbits = &sysc_regbits_omap36xx_sr,
|
||||
.mod_quirks = SYSC_QUIRK_UNCACHED,
|
||||
};
|
||||
|
||||
static const struct sysc_capabilities sysc_omap4_sr = {
|
||||
.type = TI_SYSC_OMAP4_SR,
|
||||
.regbits = &sysc_regbits_omap36xx_sr,
|
||||
};
|
||||
|
||||
/*
|
||||
* McASP register bits found on omap4 and later
|
||||
*/
|
||||
static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
|
||||
.dmadisable_shift = -ENODEV,
|
||||
.midle_shift = -ENODEV,
|
||||
.sidle_shift = 0,
|
||||
.clkact_shift = -ENODEV,
|
||||
.enwkup_shift = -ENODEV,
|
||||
.srst_shift = -ENODEV,
|
||||
.emufree_shift = -ENODEV,
|
||||
.autoidle_shift = -ENODEV,
|
||||
};
|
||||
|
||||
static const struct sysc_capabilities sysc_omap4_mcasp = {
|
||||
.type = TI_SYSC_OMAP4_MCASP,
|
||||
.regbits = &sysc_regbits_omap4_mcasp,
|
||||
};
|
||||
|
||||
/*
|
||||
* FS USB host found on omap4 and later
|
||||
*/
|
||||
static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
|
||||
.dmadisable_shift = -ENODEV,
|
||||
.midle_shift = -ENODEV,
|
||||
.sidle_shift = 24,
|
||||
.clkact_shift = -ENODEV,
|
||||
.enwkup_shift = 26,
|
||||
.srst_shift = -ENODEV,
|
||||
.emufree_shift = -ENODEV,
|
||||
.autoidle_shift = -ENODEV,
|
||||
};
|
||||
|
||||
static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
|
||||
.type = TI_SYSC_OMAP4_USB_HOST_FS,
|
||||
.sysc_mask = SYSC_OMAP2_ENAWAKEUP,
|
||||
.regbits = &sysc_regbits_omap4_usb_host_fs,
|
||||
};
|
||||
|
||||
static int sysc_init_match(struct sysc *ddata)
|
||||
{
|
||||
const struct sysc_capabilities *cap;
|
||||
|
||||
cap = of_device_get_match_data(ddata->dev);
|
||||
if (!cap)
|
||||
return -EINVAL;
|
||||
|
||||
ddata->cap = cap;
|
||||
if (ddata->cap)
|
||||
ddata->cfg.quirks |= ddata->cap->mod_quirks;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sysc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct sysc *ddata;
|
||||
int error;
|
||||
|
||||
|
|
@ -485,7 +890,15 @@ static int sysc_probe(struct platform_device *pdev)
|
|||
return -ENOMEM;
|
||||
|
||||
ddata->dev = &pdev->dev;
|
||||
ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
|
||||
platform_set_drvdata(pdev, ddata);
|
||||
|
||||
error = sysc_init_match(ddata);
|
||||
if (error)
|
||||
return error;
|
||||
|
||||
error = sysc_init_dts_quirks(ddata);
|
||||
if (error)
|
||||
goto unprepare;
|
||||
|
||||
error = sysc_get_clocks(ddata);
|
||||
if (error)
|
||||
|
|
@ -495,9 +908,24 @@ static int sysc_probe(struct platform_device *pdev)
|
|||
if (error)
|
||||
goto unprepare;
|
||||
|
||||
platform_set_drvdata(pdev, ddata);
|
||||
error = sysc_init_sysc_mask(ddata);
|
||||
if (error)
|
||||
goto unprepare;
|
||||
|
||||
error = sysc_init_idlemodes(ddata);
|
||||
if (error)
|
||||
goto unprepare;
|
||||
|
||||
error = sysc_init_syss_mask(ddata);
|
||||
if (error)
|
||||
goto unprepare;
|
||||
|
||||
pm_runtime_enable(ddata->dev);
|
||||
|
||||
error = sysc_init_module(ddata);
|
||||
if (error)
|
||||
goto unprepare;
|
||||
|
||||
error = pm_runtime_get_sync(ddata->dev);
|
||||
if (error < 0) {
|
||||
pm_runtime_put_noidle(ddata->dev);
|
||||
|
|
@ -554,16 +982,19 @@ unprepare:
|
|||
}
|
||||
|
||||
static const struct of_device_id sysc_match[] = {
|
||||
{ .compatible = "ti,sysc-omap2" },
|
||||
{ .compatible = "ti,sysc-omap4" },
|
||||
{ .compatible = "ti,sysc-omap4-simple" },
|
||||
{ .compatible = "ti,sysc-omap3430-sr" },
|
||||
{ .compatible = "ti,sysc-omap3630-sr" },
|
||||
{ .compatible = "ti,sysc-omap4-sr" },
|
||||
{ .compatible = "ti,sysc-omap3-sham" },
|
||||
{ .compatible = "ti,sysc-omap-aes" },
|
||||
{ .compatible = "ti,sysc-mcasp" },
|
||||
{ .compatible = "ti,sysc-usb-host-fs" },
|
||||
{ .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
|
||||
{ .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
|
||||
{ .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
|
||||
{ .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
|
||||
{ .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
|
||||
{ .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
|
||||
{ .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
|
||||
{ .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
|
||||
{ .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
|
||||
{ .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
|
||||
{ .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
|
||||
{ .compatible = "ti,sysc-usb-host-fs",
|
||||
.data = &sysc_omap4_usb_host_fs, },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sysc_match);
|
||||
|
|
|
|||
Loading…
Reference in a new issue