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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-25 14:13:01 -04:00
Merge "clk: qcom: gcc: Update GCC code for HOLI"
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qctecmdr
Gerrit - the friendly Code Review server
commit
fe54d0ddee
2 changed files with 94 additions and 13 deletions
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@ -127,6 +127,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_odd = {
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},
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};
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/* 1152MHz Configuration */
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static const struct alpha_pll_config gpll10_config = {
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.l = 0x3C,
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.cal_l = 0x36,
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@ -168,6 +169,7 @@ static struct clk_alpha_pll gpll10 = {
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},
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};
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/* 532MHz Configuration */
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static const struct alpha_pll_config gpll11_config = {
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.l = 0x1B,
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.cal_l = 0x25,
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@ -383,10 +385,11 @@ static struct clk_alpha_pll gpll7 = {
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},
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};
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/* 420MHz Configuration */
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static const struct alpha_pll_config gpll8_config = {
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.l = 0x1B,
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.l = 0x15,
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.cal_l = 0x2A,
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.alpha = 0xC555,
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.alpha = 0xE000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00002067,
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.test_ctl_val = 0x40000000,
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@ -447,6 +450,7 @@ static struct clk_alpha_pll_postdiv gpll8_out_even = {
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},
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};
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/* 480MHz Configuration */
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static const struct alpha_pll_config gpll9_config = {
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.l = 0x64,
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.alpha = 0x0,
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@ -988,6 +992,38 @@ static struct clk_rcg2 gcc_camss_csi2phytimer_clk_src = {
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},
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};
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static const struct freq_tbl ftbl_gcc_camss_csi3phytimer_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(133333333, P_GPLL0_OUT_ODD, 1.5, 0, 0),
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F(200000000, P_GPLL0_OUT_ODD, 1, 0, 0),
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F(268800000, P_GPLL4_OUT_EVEN, 3, 0, 0),
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{ }
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};
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static struct clk_rcg2 gcc_camss_csi3phytimer_clk_src = {
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.cmd_rcgr = 0x59054,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gcc_parent_map_4,
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.freq_tbl = ftbl_gcc_camss_csi3phytimer_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gcc_camss_csi3phytimer_clk_src",
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.parent_data = gcc_parent_data_4,
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.num_parents = 7,
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 19200000,
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[VDD_LOW] = 133333333,
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[VDD_LOW_L1] = 200000000,
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[VDD_NOMINAL] = 268800000},
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},
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};
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static const struct freq_tbl ftbl_gcc_camss_mclk0_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(24000000, P_GPLL9_OUT_MAIN, 1, 1, 20),
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@ -1135,7 +1171,7 @@ static const struct freq_tbl ftbl_gcc_camss_ope_clk_src[] = {
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F(200000000, P_GPLL8_OUT_EVEN, 2, 0, 0),
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F(266600000, P_GPLL8_OUT_EVEN, 1, 0, 0),
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F(480000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
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F(580000000, P_GPLL8_OUT_MAIN, 1, 0, 0),
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F(580000000, P_GPLL8_OUT_EVEN, 1, 0, 0),
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{ }
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};
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@ -1167,16 +1203,15 @@ static struct clk_rcg2 gcc_camss_ope_clk_src = {
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static const struct freq_tbl ftbl_gcc_camss_tfe_0_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(128000000, P_GPLL10_OUT_EVEN, 9, 0, 0),
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F(135529412, P_GPLL10_OUT_EVEN, 8.5, 0, 0),
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F(144000000, P_GPLL10_OUT_EVEN, 8, 0, 0),
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F(153600000, P_GPLL10_OUT_EVEN, 7.5, 0, 0),
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F(164571429, P_GPLL10_OUT_EVEN, 7, 0, 0),
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F(177230769, P_GPLL10_OUT_EVEN, 6.5, 0, 0),
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F(192000000, P_GPLL10_OUT_EVEN, 6, 0, 0),
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F(209454545, P_GPLL10_OUT_EVEN, 5.5, 0, 0),
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F(230400000, P_GPLL10_OUT_EVEN, 5, 0, 0),
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F(288000000, P_GPLL10_OUT_EVEN, 4, 0, 0),
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F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
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F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
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F(137142857, P_GPLL9_OUT_MAIN, 3.5, 0, 0),
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F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
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F(160000000, P_GPLL9_OUT_MAIN, 3, 0, 0),
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F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
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F(192000000, P_GPLL9_OUT_MAIN, 2.5, 0, 0),
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
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F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
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F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
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F(329142857, P_GPLL10_OUT_EVEN, 3.5, 0, 0),
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F(384000000, P_GPLL10_OUT_EVEN, 3, 0, 0),
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@ -2539,6 +2574,24 @@ static struct clk_branch gcc_camss_csi2phytimer_clk = {
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},
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};
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static struct clk_branch gcc_camss_csi3phytimer_clk = {
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.halt_reg = 0x5906c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x5906c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_camss_csi3phytimer_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_camss_csi3phytimer_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_camss_mclk0_clk = {
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.halt_reg = 0x51018,
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.halt_check = BRANCH_HALT,
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@ -2611,6 +2664,24 @@ static struct clk_branch gcc_camss_mclk3_clk = {
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},
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};
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static struct clk_branch gcc_camss_mclk4_clk = {
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.halt_reg = 0x51088,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x51088,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_camss_mclk4_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gcc_camss_mclk4_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gcc_camss_nrt_axi_clk = {
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.halt_reg = 0x58054,
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.halt_check = BRANCH_HALT,
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@ -4153,6 +4224,8 @@ static struct clk_regmap *gcc_holi_clocks[] = {
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[GCC_CAMSS_CSI1PHYTIMER_CLK_SRC] = &gcc_camss_csi1phytimer_clk_src.clkr,
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[GCC_CAMSS_CSI2PHYTIMER_CLK] = &gcc_camss_csi2phytimer_clk.clkr,
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[GCC_CAMSS_CSI2PHYTIMER_CLK_SRC] = &gcc_camss_csi2phytimer_clk_src.clkr,
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[GCC_CAMSS_CSI3PHYTIMER_CLK] = &gcc_camss_csi3phytimer_clk.clkr,
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[GCC_CAMSS_CSI3PHYTIMER_CLK_SRC] = &gcc_camss_csi3phytimer_clk_src.clkr,
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[GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr,
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[GCC_CAMSS_MCLK0_CLK_SRC] = &gcc_camss_mclk0_clk_src.clkr,
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[GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr,
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@ -4161,6 +4234,7 @@ static struct clk_regmap *gcc_holi_clocks[] = {
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[GCC_CAMSS_MCLK2_CLK_SRC] = &gcc_camss_mclk2_clk_src.clkr,
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[GCC_CAMSS_MCLK3_CLK] = &gcc_camss_mclk3_clk.clkr,
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[GCC_CAMSS_MCLK3_CLK_SRC] = &gcc_camss_mclk3_clk_src.clkr,
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[GCC_CAMSS_MCLK4_CLK] = &gcc_camss_mclk4_clk.clkr,
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[GCC_CAMSS_MCLK4_CLK_SRC] = &gcc_camss_mclk4_clk_src.clkr,
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[GCC_CAMSS_NRT_AXI_CLK] = &gcc_camss_nrt_axi_clk.clkr,
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[GCC_CAMSS_OPE_AHB_CLK] = &gcc_camss_ope_ahb_clk.clkr,
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@ -4332,6 +4406,8 @@ static const struct qcom_reset_map gcc_holi_resets[] = {
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[GCC_SDCC2_BCR] = { 0x1e000 },
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[GCC_UFS_PHY_BCR] = { 0x45000 },
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[GCC_USB30_PRIM_BCR] = { 0x1a000 },
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[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x1b020 },
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[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
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[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
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[GCC_VCODEC0_BCR] = { 0x58094 },
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[GCC_VENUS_BCR] = { 0x58078 },
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@ -198,6 +198,9 @@
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#define GCC_UFS_MEM_CLKREF_CLK 189
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#define GCC_RX5_PCIE_CLKREF_EN_CLK 190
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#define GCC_DISP_GPLL0_CLK_SRC 191
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#define GCC_CAMSS_CSI3PHYTIMER_CLK 192
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#define GCC_CAMSS_CSI3PHYTIMER_CLK_SRC 193
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#define GCC_CAMSS_MCLK4_CLK 194
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/* GCC power domains */
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#define GCC_CAMSS_TOP_GDSC 0
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@ -226,5 +229,7 @@
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#define GCC_VCODEC0_BCR 16
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#define GCC_VENUS_BCR 17
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#define GCC_VIDEO_INTERFACE_BCR 18
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#define GCC_USB3_DP_PHY_PRIM_BCR 19
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#define GCC_USB3_PHY_PRIM_SP0_BCR 20
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#endif
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