From fea29b19d8461133d45ac19a74bd683f2f178c0a Mon Sep 17 00:00:00 2001 From: Harshitha Sai Neelati Date: Fri, 20 Nov 2020 18:17:47 +0530 Subject: [PATCH] msm: kgsl: Add apb_pclk to the clock list and increase KGSL_MAX_CLKS KGSL needs to enable apb_pclk for QDSS register access. Add apb_pclk to the clock list. Increment KGSL_MAX_CLKS to support apb_pclk. Change-Id: I017628ddda2b5807aab4d8970a4ceab2d9174f53 Signed-off-by: Harshitha Sai Neelati --- drivers/gpu/msm/kgsl_pwrctrl.c | 1 + drivers/gpu/msm/kgsl_pwrctrl.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c index 28aba03c96af..44c09c3f1dec 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.c +++ b/drivers/gpu/msm/kgsl_pwrctrl.c @@ -39,6 +39,7 @@ static const char * const clocks[] = { "gmu_clk", "ahb_clk", "smmu_vote", + "apb_pclk", }; static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state, diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h index 6cfa95e809dd..c0666596617a 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.h +++ b/drivers/gpu/msm/kgsl_pwrctrl.h @@ -17,7 +17,7 @@ #define KGSL_PWR_ON 0xFFFF -#define KGSL_MAX_CLKS 17 +#define KGSL_MAX_CLKS 18 #define KGSL_MAX_PWRLEVELS 16