From ab098054720ba9b64467fa2baa661aa54d300a76 Mon Sep 17 00:00:00 2001 From: Victor Date: Fri, 5 Mar 2021 09:49:23 +0200 Subject: [PATCH 1/2] dt-bindings: arm: msm: Add UFS ICE HW Node for SA8195 and SM8150 Add required dtsi changes for UFS-ICE HW enablement for SA8195 and SM8150. Change-Id: I6183a169eef5dbb20dbdf235ce1243297431bffa --- bindings/crypto/msm/ice.txt | 51 +++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 bindings/crypto/msm/ice.txt diff --git a/bindings/crypto/msm/ice.txt b/bindings/crypto/msm/ice.txt new file mode 100644 index 000000000000..0686a21513de --- /dev/null +++ b/bindings/crypto/msm/ice.txt @@ -0,0 +1,51 @@ +* Inline Crypto Engine (ICE) + +Required properties: + - compatible : should be "qcom,ice" + - reg : + +Optional properties: + - interrupt-names : name describing the interrupts for ICE IRQ + - interrupts : + - qcom,enable-ice-clk : should enable clocks for ICE HW + - clocks : List of phandle and clock specifier pairs + - clock-names : List of clock input name strings sorted in the same + order as the clocks property. + - qocm,op-freq-hz : max clock speed sorted in the same order as the clocks + property. + - qcom,instance-type : describe the storage type for which ICE node is defined + currently, only "ufs" and "sdcc" are supported storage type + - vdd-hba-supply : regulated supply to be used by ICE HW + - qcom,bus-vector-names : bus vectors mapping + +Example: + ufs_ice: ufsice@630000 { + compatible = "qcom,ice"; + reg = <0x630000 0x8000>; + interrupt-names = "ufs_ice_nonsec_level_irq", "ufs_ice_sec_level_irq"; + interrupts = <0 258 0>, <0 257 0>; + qcom,enable-ice-clk; + clock-names = "ice_core_clk_src", "ice_core_clk"; + clocks = <&clock_gcc clk_ufs_ice_core_clk_src>, + <&clock_gcc clk_gcc_ufs_ice_core_clk>; + qcom,op-freq-hz = <300000000>, <0>; + qcom,instance-type = "ufs"; + status = "disabled"; + }; + + ufs_card_ice: ufscardice@1db0000 { + compatible = "qcom,ice_card"; + reg = <0x1db0000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&clock_gcc GCC_UFS_CARD_AXI_CLK>, + <&clock_gcc GCC_UFS_CARD_CLKREF_CLK>, + <&clock_gcc GCC_UFS_CARD_AHB_CLK>, + <&clock_gcc GCC_UFS_CARD_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_card_gdsc>; + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs_card"; + }; From f13021b9cb22d03d34bb8c06f78875d385d55765 Mon Sep 17 00:00:00 2001 From: Victor Zaharchuk Date: Sun, 28 Feb 2021 21:28:55 +0200 Subject: [PATCH 2/2] ARM: dts: msm: Add UFS ICE HW Node for SA8195 and SM8150 Add required dtsi changes for UFS-ICE HW enablement for SA8195 and SM8150. Change-Id: I0cf94e9d87cf3785ecf2d99c273694f8c44e2645 --- qcom/sdmshrike.dtsi | 16 ++++++++++++++++ qcom/sm8150.dtsi | 20 ++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/qcom/sdmshrike.dtsi b/qcom/sdmshrike.dtsi index 233b0219f67e..6333ee3f9bdf 100644 --- a/qcom/sdmshrike.dtsi +++ b/qcom/sdmshrike.dtsi @@ -1098,6 +1098,22 @@ clock-frequency = <32768>; }; + ufs_ice: ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", + "iface_clk", "ice_core_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + disp_rsc: rsc@af20000 { label = "disp_rsc"; compatible = "qcom,rpmh-rsc"; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index 6ab0bcce7f5c..3e8cba84ed8b 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -1501,6 +1501,26 @@ reg = <0x17c0000c 0x4>; }; + + + ufs_ice: ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + + apss_shared: mailbox@17c00000 { compatible = "qcom,sm8150-apss-shared"; reg = <0x17c00000 0x1000>;