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ARM: dts: msm: Update CPUFREQ-HW nodes for Blair

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Enable CPU frequency scaling and debug nodes for BLAIR.

Change-Id: I68cad665c716283298f08bb4501c7dd646dd8758
This commit is contained in:
Taniya Das 2021-04-12 19:08:12 +05:30 • committed by Madhuri Medasani
commit fee07b543a
2 changed files with 16 additions and 7 deletions
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6
qcom/blair-rumi.dtsi
View file

@ -1,4 +1,5 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-blair.h>
&soc {
timer {
clock-frequency = <500000>;
@ -149,6 +150,7 @@
&gcc {
clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&sleep_clk>;
};
&usb0 {
dwc3@4e00000 {
usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;
@ -156,3 +158,7 @@
dr_mode = "peripheral";
};
};
&cpufreq_hw {
clocks = <&bi_tcxo>, <&gcc GPLL0>;
};

17
qcom/blair.dtsi
View file

@ -68,6 +68,7 @@
dynamic-power-coefficient = <100>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -89,6 +90,7 @@
dynamic-power-coefficient = <100>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_1>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -105,6 +107,7 @@
dynamic-power-coefficient = <100>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_2>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -121,6 +124,7 @@
dynamic-power-coefficient = <100>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_3>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -137,6 +141,7 @@
dynamic-power-coefficient = <100>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_4>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -153,6 +158,7 @@
dynamic-power-coefficient = <100>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_5>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -169,6 +175,7 @@
dynamic-power-coefficient = <520>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_6>;
qcom,freq-domain = <&cpufreq_hw 1 2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -185,6 +192,7 @@
dynamic-power-coefficient = <520>;
cpu-release-addr = <0x0 0x50000000>;
next-level-cache = <&L2_7>;
qcom,freq-domain = <&cpufreq_hw 1 2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@ -1261,21 +1269,17 @@
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw-epss";
reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>,
<0x0fd04504 0x4>, <0x0fd04508 0x4>;
reg-names = "freq-domain0", "freq-domain1",
"pdmem-domain0", "pdmem-domain1";
reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
qcom,lut-row-size = <4>;
qcom,max-lut-entries = <12>;
qcom,skip-enable-check;
qcom,perf-lock-support;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int", "dcvsh1_int";
#freq-domain-cells = <2>;
status = "disabled";
};
qcom,cpufreq-hw-debug@0fd91000 {
@ -1283,7 +1287,6 @@
reg = <0x0fd91000 0x800>;
reg-names = "domain-top";
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
status = "disabled";
};
ddr_bw_opp_table: ddr-bw-opp-table {