From 48bfd0d68c0148adfab27e77a2232185ede94b57 Mon Sep 17 00:00:00 2001 From: Veera Vegivada Date: Thu, 5 Mar 2020 18:20:33 +0530 Subject: [PATCH] icc: dt-bindings: add endpoint IDs for interconnects for SM8150 Add master and slave ID constants for all Qualcomm Technologies, Inc. SM8150 interconnect providers which consumers can use to set bandwidth constraints and find paths in the NoC (Network-On-Chip) topology. Change-Id: Ie3d92159bf34e2cd57873cd3cd85c75e6a62638a Signed-off-by: Veera Vegivada --- .../dt-bindings/interconnect/qcom,sm8150.h | 161 ++++++++++++++++++ 1 file changed, 161 insertions(+) create mode 100644 include/dt-bindings/interconnect/qcom,sm8150.h diff --git a/include/dt-bindings/interconnect/qcom,sm8150.h b/include/dt-bindings/interconnect/qcom,sm8150.h new file mode 100644 index 000000000000..28a528e097e7 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm8150.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8150_H + +#define MASTER_APPSS_PROC 0 +#define MASTER_GPU_TCU 1 +#define MASTER_SYS_TCU 2 +#define MASTER_IPA_CORE 3 +#define MASTER_LLCC 4 +#define MASTER_A1NOC_CFG 5 +#define MASTER_A2NOC_CFG 6 +#define MASTER_CNOC_DC_NOC 7 +#define MASTER_GEM_NOC_CFG 8 +#define MASTER_CNOC_MNOC_CFG 9 +#define MASTER_QDSS_BAM 10 +#define MASTER_QSPI 11 +#define MASTER_QUP_0 12 +#define MASTER_QUP_1 13 +#define MASTER_QUP_2 14 +#define MASTER_SNOC_CFG 15 +#define MASTER_SPDM 16 +#define MASTER_TSIF 17 +#define MASTER_A1NOC_SNOC 18 +#define MASTER_A2NOC_SNOC 19 +#define MASTER_COMPUTE_NOC 20 +#define MASTER_CNOC_A2NOC 21 +#define MASTER_GEM_NOC_SNOC 22 +#define MASTER_GFX3D 23 +#define MASTER_MNOC_HF_MEM_NOC 24 +#define MASTER_MNOC_SF_MEM_NOC 25 +#define MASTER_NPU 26 +#define MASTER_ANOC_PCIE_GEM_NOC 27 +#define MASTER_SNOC_CNOC 28 +#define MASTER_SNOC_GC_MEM_NOC 29 +#define MASTER_SNOC_SF_MEM_NOC 30 +#define MASTER_CAMNOC_HF0 31 +#define MASTER_CAMNOC_HF0_UNCOMP 32 +#define MASTER_CAMNOC_HF1 33 +#define MASTER_CAMNOC_HF1_UNCOMP 34 +#define MASTER_CAMNOC_SF 35 +#define MASTER_CAMNOC_SF_UNCOMP 36 +#define MASTER_CRYPTO 37 +#define MASTER_ECC 38 +#define MASTER_IPA 39 +#define MASTER_MDP0 40 +#define MASTER_MDP1 41 +#define MASTER_PIMEM 42 +#define MASTER_ROTATOR 43 +#define MASTER_VIDEO_P0 44 +#define MASTER_VIDEO_P1 45 +#define MASTER_VIDEO_PROC 46 +#define MASTER_EMAC 47 +#define MASTER_GIC 48 +#define MASTER_PCIE_0 49 +#define MASTER_PCIE_1 50 +#define MASTER_QDSS_DAP 51 +#define MASTER_QDSS_ETR 52 +#define MASTER_SDCC_2 53 +#define MASTER_SDCC_4 54 +#define MASTER_UFS_CARD 55 +#define MASTER_UFS_MEM 56 +#define MASTER_USB3_0 57 +#define MASTER_USB3_1 58 +#define MASTER_SENSORS_AHB 59 +#define SLAVE_EBI1 512 +#define SLAVE_IPA_CORE 513 +#define SLAVE_A1NOC_CFG 514 +#define SLAVE_A2NOC_CFG 515 +#define SLAVE_AHB2PHY_SOUTH 516 +#define SLAVE_AOP 517 +#define SLAVE_AOSS 518 +#define SLAVE_APPSS 519 +#define SLAVE_CAMERA_CFG 520 +#define SLAVE_CLK_CTL 521 +#define SLAVE_CDSP_CFG 522 +#define SLAVE_RBCPR_CX_CFG 523 +#define SLAVE_RBCPR_MMCX_CFG 524 +#define SLAVE_RBCPR_MX_CFG 525 +#define SLAVE_CRYPTO_0_CFG 526 +#define SLAVE_CNOC_DDRSS 527 +#define SLAVE_DISPLAY_CFG 528 +#define SLAVE_EMAC_CFG 529 +#define SLAVE_GLM 530 +#define SLAVE_GFX3D_CFG 531 +#define SLAVE_IMEM_CFG 532 +#define SLAVE_IPA_CFG 533 +#define SLAVE_LLCC_CFG 534 +#define SLAVE_MSS_PROC_MS_MPU_CFG 535 +#define SLAVE_GEM_NOC_CFG 536 +#define SLAVE_CNOC_MNOC_CFG 537 +#define SLAVE_NPU_CFG 538 +#define SLAVE_PCIE_0_CFG 539 +#define SLAVE_PCIE_1_CFG 540 +#define SLAVE_NORTH_PHY_CFG 541 +#define SLAVE_PIMEM_CFG 542 +#define SLAVE_PRNG 543 +#define SLAVE_QDSS_CFG 544 +#define SLAVE_QSPI 545 +#define SLAVE_QUP_2 546 +#define SLAVE_QUP_1 547 +#define SLAVE_QUP_0 548 +#define SLAVE_SDCC_2 549 +#define SLAVE_SDCC_4 550 +#define SLAVE_SNOC_CFG 551 +#define SLAVE_SPDM_WRAPPER 552 +#define SLAVE_SPSS_CFG 553 +#define SLAVE_SSC_CFG 554 +#define SLAVE_TCSR 555 +#define SLAVE_TLMM_EAST 556 +#define SLAVE_TLMM_NORTH 557 +#define SLAVE_TLMM_SOUTH 558 +#define SLAVE_TLMM_WEST 559 +#define SLAVE_TSIF 560 +#define SLAVE_UFS_CARD_CFG 561 +#define SLAVE_UFS_MEM_CFG 562 +#define SLAVE_USB3_0 563 +#define SLAVE_USB3_1 564 +#define SLAVE_VENUS_CFG 565 +#define SLAVE_VSENSE_CTRL_CFG 566 +#define SLAVE_MNOC_SF_MEM_NOC 567 +#define SLAVE_A1NOC_SNOC 568 +#define SLAVE_A2NOC_SNOC 569 +#define SLAVE_CAMNOC_UNCOMP 570 +#define SLAVE_CDSP_MEM_NOC 571 +#define SLAVE_SNOC_CNOC 572 +#define SLAVE_CNOC_A2NOC 573 +#define SLAVE_ECC 574 +#define SLAVE_GEM_NOC_SNOC 575 +#define SLAVE_SNOC_GEM_NOC_GC 576 +#define SLAVE_SNOC_GEM_NOC_SF 577 +#define SLAVE_LLCC 578 +#define SLAVE_MNOC_HF_MEM_NOC 579 +#define SLAVE_ANOC_PCIE_GEM_NOC 580 +#define SLAVE_IMEM 581 +#define SLAVE_PIMEM 582 +#define SLAVE_SERVICE_A1NOC 583 +#define SLAVE_SERVICE_A2NOC 584 +#define SLAVE_SERVICE_CNOC 585 +#define SLAVE_SERVICE_GEM_NOC 586 +#define SLAVE_SERVICE_MNOC 587 +#define SLAVE_SERVICE_SNOC 588 +#define SLAVE_PCIE_0 589 +#define SLAVE_PCIE_1 590 +#define SLAVE_QDSS_STM 591 +#define SLAVE_TCU 592 +#define MASTER_LLCC_DISP 1000 +#define MASTER_MNOC_HF_MEM_NOC_DISP 1001 +#define MASTER_MNOC_SF_MEM_NOC_DISP 1002 +#define MASTER_MDP0_DISP 1003 +#define MASTER_MDP1_DISP 1004 +#define MASTER_ROTATOR_DISP 1005 +#define SLAVE_EBI1_DISP 1512 +#define SLAVE_MNOC_SF_MEM_NOC_DISP 1513 +#define SLAVE_LLCC_DISP 1514 +#define SLAVE_MNOC_HF_MEM_NOC_DISP 1515 + +#endif