mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-13 00:00:00 -04:00
Merge "ARM: dts: msm: Add board device-tree files for SDXLEMUR target"
This commit is contained in:
commit
ff1ba1d5d2
16 changed files with 123 additions and 1 deletions
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@ -235,6 +235,7 @@ compatible = "qcom,sdxprairie-cdp"
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compatible = "qcom,sdxlemur-rumi"
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compatible = "qcom,sdxlemur-mtp"
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compatible = "qcom,sdxlemur-cdp"
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compatible = "qcom,sdxlemur-rcm"
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compatible = "qcom,sdmmagpie-rumi"
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compatible = "qcom,sdmmagpie-idp"
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compatible = "qcom,sdmmagpie-qrd"
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@ -165,7 +165,16 @@ endif
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dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \
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sdxlemur-cdp.dtb \
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sdxlemur-mtp.dtb
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sdxlemur-mtp.dtb \
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sdxlemur-mtp-mbb.dtb \
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sdxlemur-mtp-cpe.dtb \
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sdxlemur-mtp-mbb-ntn3-pcie.dtb \
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sdxlemur-mtp-mbb-pcie-ep.dtb \
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sdxlemur-mtp-mbb-pcie-rc-ep.dtb \
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sdxlemur-mtp-mbb.dtb \
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sdxlemur-rcm-pcie-ep.dtb \
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sdxlemur-rcm-rc.dtb
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ifeq ($(CONFIG_ARCH_SHIMA), y)
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ifeq ($(CONFIG_ARCH_QTI_VM), y)
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11
qcom/sdxlemur-mtp-cpe.dts
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11
qcom/sdxlemur-mtp-cpe.dts
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@ -0,0 +1,11 @@
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/dts-v1/;
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#include "sdxlemur.dtsi"
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#include "sdxlemur-mtp-cpe.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE";
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compatible = "qcom,sdxlemur-mtp",
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"qcom,sdxlemur", "qcom,mtp";
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qcom,board-id = <0x6010008 0>;
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};
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5
qcom/sdxlemur-mtp-cpe.dtsi
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5
qcom/sdxlemur-mtp-cpe.dtsi
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@ -0,0 +1,5 @@
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&soc {
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};
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11
qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts
Normal file
11
qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts
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@ -0,0 +1,11 @@
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/dts-v1/;
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#include "sdxlemur.dtsi"
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#include "sdxlemur-mtp-mbb-ntn3-pcie.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE";
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compatible = "qcom,sdxlemur-mtp",
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"qcom,sdxlemur", "qcom,mtp";
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qcom,board-id = <0x5010008 0>;
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};
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5
qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi
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5
qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi
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@ -0,0 +1,5 @@
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&soc {
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};
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11
qcom/sdxlemur-mtp-mbb-pcie-ep.dts
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11
qcom/sdxlemur-mtp-mbb-pcie-ep.dts
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@ -0,0 +1,11 @@
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/dts-v1/;
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#include "sdxlemur.dtsi"
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#include "sdxlemur-mtp-mbb-pcie-ep.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP";
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compatible = "qcom,sdxlemur-mtp",
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"qcom,sdxlemur", "qcom,mtp";
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qcom,board-id = <0x4010008 0>;
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};
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5
qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi
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5
qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi
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@ -0,0 +1,5 @@
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&soc {
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};
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11
qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts
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11
qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts
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@ -0,0 +1,11 @@
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/dts-v1/;
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#include "sdxlemur.dtsi"
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#include "sdxlemur-mtp-mbb-pcie-rc-ep.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB RC PCIE-EP";
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compatible = "qcom,sdxlemur-mtp",
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"qcom,sdxlemur", "qcom,mtp";
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qcom,board-id = <0x3010008 0>;
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};
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5
qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi
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5
qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi
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@ -0,0 +1,5 @@
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&soc {
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};
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11
qcom/sdxlemur-mtp-mbb.dts
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11
qcom/sdxlemur-mtp-mbb.dts
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@ -0,0 +1,11 @@
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/dts-v1/;
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#include "sdxlemur.dtsi"
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#include "sdxlemur-mtp-mbb.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB";
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compatible = "qcom,sdxlemur-mtp",
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"qcom,sdxlemur", "qcom,mtp";
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qcom,board-id = <0x2010008 0>;
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};
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5
qcom/sdxlemur-mtp-mbb.dtsi
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5
qcom/sdxlemur-mtp-mbb.dtsi
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@ -0,0 +1,5 @@
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&soc {
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};
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11
qcom/sdxlemur-rcm-pcie-ep.dts
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11
qcom/sdxlemur-rcm-pcie-ep.dts
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@ -0,0 +1,11 @@
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/dts-v1/;
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#include "sdxlemur.dtsi"
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#include "sdxlemur-rcm-pcie-ep.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SDXLEMUR RCM PCIe-EP";
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compatible = "qcom,sdxlemur-rcm",
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"qcom,sdxlemur", "qcom,rcm";
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qcom,board-id = <0x1010015 0>;
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};
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5
qcom/sdxlemur-rcm-pcie-ep.dtsi
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5
qcom/sdxlemur-rcm-pcie-ep.dtsi
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@ -0,0 +1,5 @@
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&soc {
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};
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11
qcom/sdxlemur-rcm-rc.dts
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11
qcom/sdxlemur-rcm-rc.dts
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@ -0,0 +1,11 @@
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/dts-v1/;
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#include "sdxlemur.dtsi"
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#include "sdxlemur-rcm-rc.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex";
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compatible = "qcom,sdxlemur-rcm",
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"qcom,sdxlemur", "qcom,rcm";
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qcom,board-id = <0x1010015 0>;
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};
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5
qcom/sdxlemur-rcm-rc.dtsi
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5
qcom/sdxlemur-rcm-rc.dtsi
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@ -0,0 +1,5 @@
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&soc {
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};
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