From ff94236a3ab5b04c73c0b4cc465d9cfd34eb4582 Mon Sep 17 00:00:00 2001 From: Dhaval Patel Date: Mon, 15 Jun 2020 10:14:50 -0700 Subject: [PATCH] ARM: dts: msm: update irq latency for mdss irq on lahaina target Update irq latency node for lahaina target in SDE driver for mdss irq. Change-Id: Id19d3abd34454d1a8d1e43a7a0bc62daa750011c --- bindings/sde.txt | 2 ++ display/lahaina-sde.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/bindings/sde.txt b/bindings/sde.txt index cf824c15d47d..423532d1ac04 100644 --- a/bindings/sde.txt +++ b/bindings/sde.txt @@ -473,6 +473,7 @@ Optional properties: 0xf represents 4 cpu cores. These cores can be silver or gold or gold+. - qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec. +- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec. - qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline rotation. - qcom,sde-inline-rot-xin-type: A string array indicating the type of xin, @@ -740,6 +741,7 @@ Example: qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-mask-performance = <0xf>; qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; qcom,sde-vbif-off = <0 0>; qcom,sde-vbif-id = <0 1>; diff --git a/display/lahaina-sde.dtsi b/display/lahaina-sde.dtsi index a48726e69e2f..66286ea86fee 100644 --- a/display/lahaina-sde.dtsi +++ b/display/lahaina-sde.dtsi @@ -232,6 +232,7 @@ qcom,sde-qos-cpu-mask = <0x3>; qcom,sde-qos-cpu-dma-latency = <300>; + qcom,sde-qos-cpu-irq-latency = <300>; /* offsets are relative to "mdp_phys + qcom,sde-off */