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cpufreq: qcom-hw: Add register offsets for non-epss devices

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Update the cpufreq hardware register offsets data for non EPSS devices to
be able to parse the LUTs of frequency and voltage.

Re-introduce the commit '00319840a4af ("cpufreq: qcom-hw: Update freq_scale
from fast_switch path")'
The freq_scale maintained by the topology driver needs to be updated when
the frequency is transitioned. Without this, the current capacity of a CPU
metric gets broken in the scheduler.

The current code calls arch_set_freq_scale() from the target_index method
but not from the fast_switch method. Fix this.

Change-Id: I2789b76f14b4c0fe8ad52b449ed9f4ea3a4bff32
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2019-05-20 14:55:29 +05:30 • committed by Gerrit - the friendly Code Review server
commit ffd89c1cb1
1 changed files with 11 additions and 5 deletions
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16
drivers/cpufreq/qcom-cpufreq-hw.c
View file

@ -48,6 +48,14 @@ struct cpufreq_counter {
};
static const u16 cpufreq_qcom_std_offsets[REG_ARRAY_SIZE] = {
[REG_ENABLE] = 0x0,
[REG_FREQ_LUT_TABLE] = 0x110,
[REG_VOLT_LUT_TABLE] = 0x114,
[REG_PERF_STATE] = 0x920,
[REG_CYCLE_CNTR] = 0x9c0,
};
static const u16 cpufreq_qcom_epss_std_offsets[REG_ARRAY_SIZE] = {
[REG_ENABLE] = 0x0,
[REG_FREQ_LUT_TABLE] = 0x100,
[REG_VOLT_LUT_TABLE] = 0x200,
@ -55,7 +63,6 @@ static const u16 cpufreq_qcom_std_offsets[REG_ARRAY_SIZE] = {
[REG_CYCLE_CNTR] = 0x3c4,
};
static struct cpufreq_counter qcom_cpufreq_counter[NR_CPUS];
static struct cpufreq_qcom *qcom_freq_domain_map[NR_CPUS];
@ -128,7 +135,6 @@ static unsigned int
qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
unsigned int target_freq)
{
struct cpufreq_qcom *c = policy->driver_data;
int index;
index = policy->cached_resolved_idx;
@ -243,12 +249,12 @@ static int qcom_cpufreq_hw_read_lut(struct platform_device *pdev,
base_volt = c->reg_bases[REG_VOLT_LUT_TABLE];
for (i = 0; i < LUT_MAX_ENTRIES; i++) {
data = readl_relaxed(base_freq + i * LUT_ROW_SIZE);
data = readl_relaxed(base_freq + i * lut_row_size);
src = (data & GENMASK(31, 30)) >> 30;
lval = data & GENMASK(7, 0);
core_count = CORE_COUNT_VAL(data);
data = readl_relaxed(base_volt + i * LUT_ROW_SIZE);
data = readl_relaxed(base_volt + i * lut_row_size);
volt = (data & GENMASK(11, 0)) * 1000;
if (src)
@ -465,7 +471,7 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
static const struct of_device_id qcom_cpufreq_hw_match[] = {
{ .compatible = "qcom,cpufreq-hw", .data = &cpufreq_qcom_std_offsets },
{ .compatible = "qcom,cpufreq-hw-epss",
.data = &cpufreq_qcom_std_offsets },
.data = &cpufreq_qcom_epss_std_offsets },
{}
};