From 821b9fac955178b8f6b5b97faee6ffd1d933d78c Mon Sep 17 00:00:00 2001 From: Siva Kumar Akkireddi Date: Tue, 30 Jun 2020 02:06:57 +0530 Subject: [PATCH] msm: ep_pcie: Correct clkreq override value Use unshifted value to set the clock req override value and enable fields as the register write function already shifts the values to the correct position. Change-Id: I0b5dea0f6f8462363471910ffe93f8f8975e7929 Signed-off-by: Siva Kumar Akkireddi Signed-off-by: Veerabhadrarao Badiganti --- drivers/platform/msm/ep_pcie/ep_pcie_com.h | 8 ++++++-- drivers/platform/msm/ep_pcie/ep_pcie_core.c | 12 ++++++++---- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h index db676c486ea3..bb5d581a8ba9 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h +++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h @@ -47,9 +47,13 @@ #define PCIE20_PARF_CLKREQ_OVERRIDE 0x2B0 #define PCIE20_PARF_CLKREQ_IN_OVERRIDE_STS BIT(5) #define PCIE20_PARF_CLKREQ_OE_OVERRIDE_STS BIT(4) -#define PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL BIT(3) +#define PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_MASK BIT(3) +#define PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_ASSERT 0 +#define PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_DEASSERT 1 #define PCIE20_PARF_CLKREQ_OE_OVERRIDE_VAL BIT(2) -#define PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE BIT(1) +#define PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_MASK BIT(1) +#define PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_DIS 0 +#define PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_EN 1 #define PCIE20_PARF_CLKREQ_OE_OVERRIDE_ENABLE BIT(0) #define PCIE20_PARF_SLV_ADDR_MSB_CTRL 0x2C0 diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index 6c7b7e1291f5..6468591480ef 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -1440,14 +1440,18 @@ static int ep_pcie_core_clkreq_override(bool config) if (config) { ep_pcie_write_reg_field(dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE, - PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL, BIT(3)); + PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_MASK, + PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_DEASSERT); ep_pcie_write_reg_field(dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE, - PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE, BIT(1)); + PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_MASK, + PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_EN); } else { ep_pcie_write_reg_field(dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE, - PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE, 0); + PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_MASK, + PCIE20_PARF_CLKREQ_IN_OVERRIDE_ENABLE_DIS); ep_pcie_write_reg_field(dev->parf, PCIE20_PARF_CLKREQ_OVERRIDE, - PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL, 0); + PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_MASK, + PCIE20_PARF_CLKREQ_IN_OVERRIDE_VAL_ASSERT); } return 0;