- fix cmap leak in removal path
- fix cmap leak when register_framebuffer fails
- check return value of fb_alloc_cmap
- don't continue with driver setup if register_framebuffer fails
[[email protected]: spotted missing iounmap]
[[email protected]: move data declaration before any code]
Signed-off-by: Andres Salomon <[email protected]>
Cc: Krzysztof Helt <[email protected]>
Signed-off-by: Randy Dunlap <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
The s1d13xxx chip provides two values of identification value: the
Production id (e.g 13506/13505/13806..) and a revision number 0,1,2,3).
Together these can help us to differentiate between similiar setups.
This patch adds the proper way of grabbing both those values and save them
for future reference (in order to decide what functions a card supports,
e.g acceleration).
We also move away from the concept of all s1d13xxx = s1d13806 when we
really support alot more.
[[email protected]: coding-style fixes]
[[email protected]: simplify s1d13xxxfb_probe()]
Signed-off-by: Kristoffer Ericson <[email protected]
Cc: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
- fix cmap leak in removal path
- fix cmap leak when register_framebuffer fails
- check return value of fb_alloc_cmap
Signed-off-by: Andres Salomon <[email protected]>
Acked-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Fix a circular locking dependency in the frame buffer console driver
pushing down the mutex fb_info->lock.
Circular locking dependecies occur calling the blocking
fb_notifier_call_chain() with fb_info->lock held. Notifier callbacks can
try to acquire mm->mmap_sem, while fb_mmap() acquires the locks in the
reverse order mm->mmap_sem => fb_info->lock.
Tested-by: Andrey Borzenkov <[email protected]>
Signed-off-by: Andrea Righi <[email protected]>
Cc: Geert Uytterhoeven <[email protected]>
Cc: Krzysztof Helt <[email protected]>
Cc: <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Fix threshold register mask for Laguna chips otherwise some 8bpp modes are
garbled after selecting a 24bpp mode.
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Fix handling of the Cirrus Logic GD5434 chip. Distinguish this chip from the
GD5430. It allows detecting memory size for both models correctly.
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
A memory clock (MCLK) is set at various places. Move the setting into one
place.
Set the MCLK only for Zorro cards as the x86 cards should be initialized by
BIOS.
Improve handling of the GD5434 (SD64).
Kill one annoying debug output "virtual offset: ...".
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Add an accelerator constant so almost all Cirrus are recognized as
accelerators by the fbset command.
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Cirrus' Alpine and Picasso4 chips uses DAC clock doubling to achieve full
range of pixclock frequencies.
[[email protected]: fix spelling, use usual comment layout]
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
The 32bpp is supported only on the latest Cirrus Logic chips. Use the
24bpp which is supported at least since Alpine chips (GD543x).
Change 32bpp mode setting to 24bpp mode. Change acceleration as well.
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Various fixes to make Cirrus GD5446 chip work.
Another Cirrus chip works with the cirrusfb. The gd5446 seems very
similar to Alpine chips.
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Balance iomap and iounmap and alloc and free calls in case of error druing
device register (probing).
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Add hardware color expansion (imageblit) function. It roughly doubles
scrolling speed of my Alpine card (GD5430).
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
- Fix color expansion for 16bpp and 32bpp modes in the
cirrusfb_RectFill().
- Make a function with a common blitter code (cirrusfb_set_blitter).
- Add fb_sync function to allow a higher layer synchronize with the
blitter.
- Kill one redundant blitter reset.
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
- The Laguna GD5465 (AGP) has one register more than non-AGP chips.
Recognize the AGP version and write a tile control register only on the
AGP version. Tested only on an AGP card.
- Bump up RAMDAC frequencies after X11 code. This allow to drive a flat
panel resolution 1680x1050 at 16bpp from the 4MB card.
- Fix screen start address overflow bits on Laguna cards (CRT1D
register).
- Fix exit path in the cirrusfb_pci_register() in case of error.
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Break cirrusfb_decode_var() function into two parts:
cirrusfb_check_pixclock() which can be called from the
cirrusfb_check_var() aand merge rest into the cirrusfb_set_par_foo().
This allows rejecting modes with too high pixclock before before any
change to hardware state (and a console is messed up).
Also, fix RGB field's lengths for 8bpp modes to correct ones so X11 works
with fbdev driver with cirrusfb.
Kill some redundant function calls or register loads.
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Fix 8bpp mode by adding handling of the Laguna chipsets to various places
and stop trashing a HDR register which probably does not exist on the
Laguna.
Fix compilation warnings about uninitialized variables also.
Finally, all 8bpp, 16bpp and 32bpp modes work on the Laguna chipset.
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Various improvements to the code:
- kill a structure with only one
field: multiplexing and use the
field directly
- move the cirrusfb_ops structure
down the file to kill forward
declarations
- move cirrusfb_init() to kill
forward declaration
- kill register loads done already
in the init_vgachip()
- kill assigments done by higher
layer in the cirrusfb_pan_display()
- do not overwrite line pitch bit in
the CL_CRT1D register
- kill btype variables if they were
used only once or twice
- add cpu_relax() in the busy waiting
loop
The fix to the CL_CRT1D register handling makess the 1024x768 32bpp mode
work. Previously, only lower resolution modes have worked with 32bpp.
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Use the 5-6-5 RGB mode instead of the 5-5-5 mode at 16bpp depth.
It fixes colors in the 16bpp modes on Cirrus Laguna chips.
Signed-off-by: Krzysztof Helt <[email protected]>
Cc: Geert Uytterhoeven <[email protected]>
Cc: Arthur Marsh <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
A line length is calculated twice: first in the cirrusfb_decode_var() then
in the cirrusfb_set_par_foo().
Use the first calculated value. A nice side effect is that 32bpp mode
works now.
Signed-off-by: Krzysztof Helt <[email protected]>
Cc: Geert Uytterhoeven <[email protected]>
Cc: Arthur Marsh <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
The Laguna chipsets use special registers which are available through the
mmio area. The cirrusfb driver does not use memory mapped registers for
the PCI cards.
Add the memory mapped area for Laguna chipsets and add basic usage of the
special Laguna registers after SVGALIB code.
This gives readable console at 16bpp on the GD-5465 (Laguna AGP). The
8bpp and 32bpp depths are still broken.
Signed-off-by: Krzysztof Helt <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Add additional overflow register setting for Laguna chips.
Also, simplify some code in the cirrusfb_pan_display() and
cirrusfb_blank().
Signed-off-by: Krzysztof Helt <[email protected]>
Cc: Geert Uytterhoeven <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Fix memory detection and clock setting for Cirrus Laguna chipsets
(GD5464/GD5465). The changes are done after the Xorg code.
The driver still does not display anything on the GD5465 but it switches
resolutions correctly at least.
Signed-off-by: Krzysztof Helt <[email protected]>
Cc: Geert Uytterhoeven <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
Add support for the EPSON RX8025 RTC. The date/time registers of this
chip are compatible with the DS1307.
Signed-off-by: Matthias Fuchs <[email protected]>
Signed-off-by: Alessandro Zummo <[email protected]>
Cc: David Brownell <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
