Different GPU can have a different GMEM size so need to configure
UCHE GMEM base address accordingly. Having a fix base as 0x100000
results in RB and UCHE GMEM range overlap on GPUs with GMEM size >1MB.
Also, adjust SVM 32bit base based on GMEM UCHE range end to prevent
GMEM UCHE and SVM 32bit range overlap.
Change-Id: I41330a33b79bf8c79b593ecd89593a796230b074
Signed-off-by: Deepak Kumar <[email protected]>
The version numbers shall be copied into the local variables for
any potential version comparison.
Change-Id: I08ac6359df0890a2605dbb6279b73abe09060ec8
Signed-off-by: Yong Ding <[email protected]>
The prink() could consume enough CPU when the retry eventually takes
a lot of times before it could succeed.
Change-Id: I4f49d0650ee3ae06700d2ce592acd0532bbf38cd
Signed-off-by: Yong Ding <[email protected]>
Since for the Genoa or the SP that doesn't need
regdb.bin for Hasting, it should happen search
regdb.bin failure issue that cause 60s timeout.
So add one compile macro CNSS_REQ_FW_DIRECT to
replace request_firmware_direct with request_
firmware for regdb.bin and only search the folder
that set by fw_path, which can avoid 60s timeout
while search file failure in the user space.
static const char * const fw_path[] = {
fw_path_para,
"/lib/firmware/updates/" UTS_RELEASE,
"/lib/firmware/updates",
"/lib/firmware/" UTS_RELEASE,
"/lib/firmware"
};
Above piece of code is the definition of fw_path
from drivers/base/firmware_loader/main.c.
Change-Id: I79c2fce33a8befecb0242a70b7eee1eef9a76e9b
Signed-off-by: Chaoli Zhou <[email protected]>
Signed-off-by: Kuichu Ni <[email protected]>
Currently power_role is accessed by set_prop and get_prop
functions of typec_power_role without any locking mechanism,
there can be a scenario where both function calls were invoked
simultaneously and power_role variable is not correctly
updated, and it leads to enumeration issues when connected to PC.
Fix it by adding locking mechanism to power_role.
Change-Id: I4f5dc38a9536b535510dc2b112712a5cbd2b3f84
Signed-off-by: Kavya Nunna <[email protected]>
In the process of idle shutdown, cnss_pci_power_off_mhi()
already done with CNSS_MHI_POWER_OFF state set, but
cnss_suspend_pci_link() doesn't complete yet, so PCI_LINK_DOWN
won't be set, at the same time system suspend comes, it will be
failed with CNSS_MHI_SUSPEND state set checking at
cnss_pci_suspend_bus()/cnss_pci_set_mhi_state().
When mhi state is already CNSS_MHI_POWER_OFF, no need to do pci
suspend link related operation while such actions also will be done
through cnss_qca6290_shutdown()/cnss_suspend_pci_link(). Fix is to
check CNSS_MHI_POWER_OFF state in cnss_pci_suspend_bus().
Change-Id: I2e03dffdc29b5c9743209cbd29c16345d414af35
Signed-off-by: Huashan Qu <[email protected]>
Only when SMMU S1 enabled, CNSS driver will send IOVA range in
HOST_CAP message, and let firmware to configure ATU.
Change-Id: Idd19063da975c0105d91e0e31575d0b0d1edd8e2
Signed-off-by: Lin Bai <[email protected]>
Currently CNSS2 driver does not support multi chips. This is a update of
the CNSS2 driver to support multi chips with converged dts.
Change-Id: Ie3efb526220c2de21e021320322d46c345d770bc
Signed-off-by: wei yang <[email protected]>
Signed-off-by: Kuichu Ni <[email protected]>
Remove all the leading and trailing whitespaces in the string copied
from userspace.
Change-Id: I627416dcdb1155303ad6a8ed172910a8653dd67b
Signed-off-by: Jay Jayanna <[email protected]>
Improve the api to better handle certain error scenarios
and move console prints outside of irq/locked code
sections.
Change-Id: I0ec6f37400949c014ea2e94f61a239294c954bf5
Signed-off-by: Neeraj Upadhyay <[email protected]>
On certain platforms, due to a HW issue, the SSPHY keeps
transitioning in and out of p3 whenever we perform any HS
transfers. This leads to a storm of PWR_EVNT irgs.
Fix this by disabling SSPHY autosuspend on such platforms.
Autosuspend will be enabled as part of dwc3_msm_prepare_suspend
so that SSPHY gets a chance to go into P3.
Change-Id: I4e674f780a72a8c4abcb3e6c9f083f23b1faa196
Signed-off-by: Aniket Randive <[email protected]>
In line with the sequence for primary port, update proper fields
of DWC3_GUSB2PHYCFG and DWC3_GUSB3PIPECTL registers for the
second port of the dual port controller. Update other registers
as required.
While at it, also avoid enabling SSPHY autosuspend if
dis_u3_susphy_quirk is set.
Change-Id: Ib79dba4c6d854fa2bf33a1b7cecf06f988250662
Signed-off-by: Ajay Agarwal <[email protected]>
Signed-off-by: Harsh Agarwal <[email protected]>
Certain targets may have a dual port capable host controller.
Add support for the PHY IRQs for the second port. Since the SSPHY
autosuspend will be disabled for such controllers, remove the
support of pwr_evnt_irq as a mandatory IRQ and allow SSPHY to go
into P3 as a part of suspend sequence. Handle the logic
gracefully to maintain single port controllers.
Change-Id: I5a53d6e23f64bec7ae940d23923df310309a28da
Signed-off-by: Ajay Agarwal <[email protected]>
Signed-off-by: Harsh Agarwal <[email protected]>
Add 2 new PHY instances (HS and SS) in dwc3 and dwc3-msm
structures. Probe and initialize them when the controller is
dual port capable. This capability is advertised by cores
supporting only host mode using the DT flag 'qcom,dual-port'.
Update PHY1 flags wherever applicable while maintaining single
port controller support.
Avoid workaround of SSPHY powerdown as a part of HS device
connect because of the known HW issue of the other SSPHY going in
and out of P3 when data transfers are being done.
Change-Id: If52fd6383cc2da8b763c774d2ad688448f90aea0
Signed-off-by: Ajay Agarwal <[email protected]>
Signed-off-by: Harsh Agarwal <[email protected]>
Download qdss cfg file at end of fw mem ready handler instead
of downloading cfg file after fw init done. Wlan fw expects
qdss mem req/resp from host before mode on request from it.
Wlan fw will wait for qdss memory sync qmi exchange from
host before sending fw init done to it to avoid receiving
qdss memory sync after mode on request.
Change-Id: If4e752c398821a5cdfeb1b5aeaf735f1973b5635
Signed-off-by: Sandeep Singh <[email protected]>
Add initial driver to support pin configuration with
pinctrl framework for Direwolf SoC.
Change-Id: I7fd92e716eec71fc0cbdced54902f2ddfadedcc0
Signed-off-by: Shreyas K K <[email protected]>
Add snapshot of vm power off driver as of msm-4.14
'commit 77a20e0a50e1
("power: reset: cache flush before VM restart")'.
Change-Id: I380b16f46429711284bb6717847a1eef5d8ee9b1
Signed-off-by: Ping Jiang <[email protected]>
In kgsl_ioctl_gpu_aux_command, kgsl_gpu_aux_command_generic struct
is copied to kernel before calling into kgsl_drawobj_add_timeline
and it is copied again inside kgsl_drawobj_add_timeline as part of
get_aux_command. Avoid this by directly passing user pointer and
size need by kgsl_drawobj_add_timeline to get the timeline command
struct.
Change-Id: Ic6e4e8a79484c85070f1feda516bbb0c0ace83eb
Signed-off-by: Deepak Kumar <[email protected]>
disable CONFIG_RPMSG_QCOM_GLINK_SPI config for auto target.
Change-Id: I762e5edafc39f5c2ff4a082e2b254b12a9a5fa13
Signed-off-by: Ashish Kori <[email protected]>
During SSR testing, subsystem and qmi notifications for SSR/PDR
sequence is missing sometimes. We are seeing 2 times DOWN notification
without UP. This will lead to imbalance in disabling and enabling of
core IRQ and capability exchange is timing out.
If interrupt line is not enabled, during retry-capability exchange
request is timing out and leading to freed memory access
inside ngd_xfer_msg.
Fix this issue by removing enabling and disabling from ngd_slim_enable
enable it only once during probe.
Change-Id: I15616c6e284848ed1f2aca00d251b82f79feb803
Signed-off-by: Chandana Kishori Chiluveru <[email protected]>
In this case, CONFIG_SMP and CONFIG_LPAE are both not enabled,
CONFIG_ENABLE_VMALLOC_SAVING is enabled. The paddr|size|addr
satisfies PMD_SIZE alignment, will create section mapping not
page mapping, non-LPAE arm32 uses 2-level page table, including
pgd and pte, before remapping it will do unmapping which clears
init_mm->pgd of corresponding addr and memcpy into [VMALLOC_START,
VMALLOC_END) part of current->active_mm->pgd, but this memcpy misses
to sync other vmalloc areas outside [VMALLC_START, VMALLOC_END) with
vmalloc saving feature, the pgd part of addr in other vmalloc
areas is not synced and still holds the stale mappings, if request
addrs fall into other vmalloc areas, then page fault happens for them.
So need to consider other vmalloc areas outside [VMALLOC_START,
VMALLOC_END) with vmalloc saving feature, change into [PAGE_OFFSET,
VMALLOC_END) to include all vmalloc areas, then all pgds of vmalloc
addrs in current->active_mm->pgd will be synced on unmapping, the
pgds of request addrs are cleared, then do_traslation_fault will
be called for zero pgd value, it calls copy_pmd to sync the pgds
from init_mm->pgd to current->active_mm->pgd for request addrs on
remapping.
Change-Id: Ia283d409a20c8fc9951434078332a3badf0f9ed0
Signed-off-by: Qingqing Zhou <[email protected]>
Avg_current is an unsigned 16-bit data and assigning it a negative
value would make it being shown as a very big positive value which
doesn't make sense for ECM current measurement. Instead, assign it
to 0 upon error exceptions and print out corresponding messages.
Change-Id: I438667e40d63e4142860b7de4e7cf7495d3c424e
Signed-off-by: Fenglin Wu <[email protected]>
Add ebi2 support to GPIO 89 and 90 and add an ebi2_a function.
Change-Id: I1854aea3011b1d1cf67ebfebddb1c6b60a34a1b1
Signed-off-by: Melody Olvera <[email protected]>
QCA6390 requires synchronization between BT and WLAN enable gpio
to avoid power up issue. Add support for QCA6390 in gpio sync
code.
Change-Id: Id2183ff324c9c3059ea81e9137fa49c803feb183
Signed-off-by: Mohammed Siddiq <[email protected]>
Enable SCHED_WALT to add support for scheduler
features like WALT, core_ctl, etc.
Change-Id: I7a3c4494b5c2e6545821491e1aee8bf6c4ac3345
Signed-off-by: Shreyas K K <[email protected]>
Enable SCHED_WALT to add support for scheduler
features like WALT, core_ctl, HMP, etc.
Change-Id: I0b4efd6e2127771be65c754fa35770ba359576bd
Signed-off-by: Shreyas K K <[email protected]>
