Reported by smatch:
amdgpu_dm.c:5637 amdgpu_dm_commit_planes() error: we previously assumed 'acrtc_state->stream' could be null
This seems to be checked for null pretty consistently elsewhere.
Signed-off-by: Ernst Sjöstrand <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Reported by smatch:
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:1496 amdgpu_hwmon_show_temp() error: uninitialized symbol 'temp'.
Signed-off-by: Ernst Sjöstrand <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Reported by smatch:
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c:693 amdgpu_set_pp_od_clk_voltage() error: uninitialized symbol 'ret'.
Signed-off-by: Ernst Sjöstrand <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Reported by smatch:
drivers/gpu/drm/amd/amdgpu/soc15.c:715 soc15_get_pcie_usage() warn: inconsistent indenting
And a similar one in si.c.
Signed-off-by: Ernst Sjöstrand <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
No need to protect the comments. The DCN1_01 config
was dopped anyway. Got accidently brought back with the
navi merge.
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
We may need to sleep for up to 80ms
(8ms per each of up to 10 loop iterations):
/* First DPCD read after VDD ON can fail if the particular board
* does not have HPD pin wired correctly. So if DPCD read fails,
* which it should never happen, retry a few times. Target worst
* case scenario of 80 ms.
*/
Switch udelay to msleep to avoid limits on arm.
Reviewed-by: Nicholas Kazlauskas <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Use drm_atomic_helper_dirtyfb() as the dirty callback in the
msm_framebuffer_funcs struct. Call drm_plane_enable_fb_damage_clips()
when the planes are initialized in mdp4, mdp5, and dpu1.
Signed-off-by: Brian Masney <[email protected]>
Signed-off-by: Rob Clark <[email protected]>
The Demand Prefetch workaround (binding table prefetching) only applies
to Icelake A0/B0. But the Sampler Prefetch workaround needs to be
applied to all Gen11 steppings, according to a programming note in the
SARCHKMD documentation.
Using the Intel Gallium driver, I have seen intermittent failures in
the dEQP-GLES31.functional.copy_image.non_compressed.* tests. After
applying this workaround, the tests reliably pass.
v2: Remove the overlap with a pre-production w/a
BSpec: 9663
Signed-off-by: Kenneth Graunke <[email protected]>
Signed-off-by: Chris Wilson <[email protected]>
Cc: [email protected]
Reviewed-by: Mika Kuoppala <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
DisplayID blocks allow embedding of CEA blocks. The payloads are
identical to traditional top level CEA extension blocks, but the header
is slightly different.
This change allows the CEA parser to find a CEA block inside a DisplayID
block. Additionally, it adds support for parsing the embedded CTA
header. No further changes are necessary due to payload parity.
This change fixes audio support for the Valve Index HMD.
Signed-off-by: Andres Rodriguez <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Cc: Jani Nikula <[email protected]>
Cc: <[email protected]> # v4.15
Signed-off-by: Dave Airlie <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
This contains a couple of small improvements and cleanups for the Tegra
DRM driver.
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Merge tag 'drm/tegra/for-5.3-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next
drm/tegra: Changes for v5.3-rc1
This contains a couple of small improvements and cleanups for the Tegra
DRM driver.
Signed-off-by: Dave Airlie <[email protected]>
From: Thierry Reding <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
These regs are write-only, and the hw throws a hissy-fit (ie. reboots)
when we try to read them for GPU state snapshot, in response to a GPU
hang. It is rather impolite when GPU recovery triggers an insta-
reboot, so lets remove the TPL1 registers from the snapshot.
Fixes: 7198e6b031 drm/msm: add a3xx gpu support
Signed-off-by: Rob Clark <[email protected]>
Reviewed-by: Jordan Crouse <[email protected]>
For uvd_4/5/6, amdgpu driver will only power on them when
there are jobs assigned to decode/enc rings.uvd_4/5/6 dpm was broken
since amdgpu_dpm_set_powergating_by_smu only covers gfx block.
The change would add more IP block support in amdgpu_dpm_set_powergating_by_smu
For GFX/UVD/VCN/VCE, if the new SMU driver is supported, invoke new
power gate helper function smu_dpm_set_power_gate, otherwise, fallback to
legacy powerplay helper function pp_set_powergating_by_smu. For other IP blocks
always invoke legacy powerplay helper function.
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Tianci Yin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
In the unlikely case (thank you CI!), we may find ourselves wanting to
issue a preemption but having no runnable requests left. In this case,
we set the semaphore before computing the preemption and so must unset
it before forgetting (or else we leave the machine busywaiting until the
next request comes along and so likely hang).
v2: Replace readback with only a wmb after asserting the semaphore
Signed-off-by: Chris Wilson <[email protected]>
Cc: Mika Kuoppala <[email protected]>
Reviewed-by: Mika Kuoppala <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
It was replaced with the sw_init callback so is no longer
needed.
Reviewed-by: Felix Kuehling <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
change df_init to df_sw_init df 1.7 to prevent regression issues on pre-vega20
products when callback is called in sw_common_sw_init.
Reviewed-by: Felix Kuehling <[email protected]>
Signed-off-by: Jonathan Kim <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Previous kfd doesn't use gws so this mask was set to 0.
Set it to 64 bit 1s because now kfd can use all 64 gws
resources.
Signed-off-by: Oak Zeng <[email protected]>
Reviewed-by: Felix Kuehling <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
during navi10 bring up, dwb causes system hang.
to continue debug major issue, disable dwb by
set num-dwb = 0. the hang issue is not reproduced now
by enable num-dwb =1. dc source is shared by all os.
win needs num-dwb = 1.
Signed-off-by: hersen wu <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Reviewed-by: Roman Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[why]
Before for raven and navi we are calling pp_smu functions for pme
[how]
refactor a code so we will call clk_mgr's enable_pme_wa function so we
can use pme_wa for future asics. This way we don't need to worry about
different ASIC since clk_mgr already have that information
Signed-off-by: Su Sung Chung <[email protected]>
Reviewed-by: Eric Yang <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
For debugging underflow issues it can be useful to have asserts when the
underflow initially occurs.
[How]
Read the underflow status registers after actions that have a high risk
of causing underflow and assert that no underflow occurred. If underflow
occurred, clear the bit.
Signed-off-by: Thomas Lim <[email protected]>
Reviewed-by: Eric Yang <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Currently vmid is decided internally inside dc. With the introduction
of new asics we are required to coordinate vmid use with external
components.
This change converts vmid logic to a DAL module allowing vmid to be
passed in as a parameter to DC.
Signed-off-by: Dmytro Laktyushkin <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[why]
value commited to by HW team is going to be higher
than pre-silicon, and will cause underflow if driver not
updated
[how]
update hardcoded value, update pstate switching logic
to fix case where with long uclk time we won't allow switch
even when we should
Signed-off-by: Jun Lei <[email protected]>
Reviewed-by: Eric Yang <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
To prepare for the upcoming DRM plane color management properties
we need to correct a lot of wrong behavior and assumptions made for
CRTC color management.
The documentation added by this commit in amdgpu_dm_color explains
how the HW color pipeline works and its limitations with the DRM
interface.
The current implementation does the following wrong:
- Implicit sRGB DGM when no CRTC DGM is set
- Implicit sRGB RGM when no CRTC RGM is set
- No way to specify a non-linear DGM matrix that produces correct output
- No way to specify a correct RGM when a linear DGM is used
We had workarounds for passing kms_color tests but not all of the
behavior we had wrong was covered by these tests (especially when
it comes to non-linear DGM). Testing both DGM and RGM at the same time
isn't something kms_color tests well either.
[How]
The specifics for how color management works in AMDGPU and the new
behavior can be found by reading the documentation added to
amdgpu_dm_color.c from this patch.
All of the incorrect cases from the old implementation have been
addressed for the atomic interface, but there still a few TODOs for
the legacy one.
Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI.
The result looks correct from visual inspection but the CRC no longer
matches. For reference, the test was previously doing the following:
linear degamma -> CTM -> sRGB regamma -> RGB to YUV (709) -> ...
Now the test is doing:
linear degamma -> CTM -> linear regamma -> RGB to YUV (709) -> ...
Signed-off-by: Nicholas Kazlauskas <[email protected]>
Reviewed-by: Sun peng Li <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[WHY]
This is meant to make it clearer that 0xf is not a valid OPP ID, and
that code making use of OPP IDs should not accept this value.
Signed-off-by: Wesley Chalmers <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
expose this function for future use
Implementation of DCN3 DIO Link Encoder including
dpcs register headers.
Signed-off-by: Eric Bernstein <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[why]
Existing behavior has overlapping ranges resulting in path
dependent SMU selection
[how]
Make ranges non-overlapping, resulting in non-path dependent
selection
Signed-off-by: Jun Lei <[email protected]>
Reviewed-by: Eric Yang <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[why]
According to the latest specs, the max_target bpp sink
can support is 16 bpp.
[how]
update dsc max_target_bpp to 16
Signed-off-by: Wenjing Liu <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[why]
Current policy assumes virtual DPCD peer device as
an individual MST branch device with 1 input and 1 output.
However this is only true for virtual DP-to-DP peer device.
In general there are three types of virtual DP peer devices.
1. Sink peer device with virtual DPCD.
2. Virtual DP-to-DP Peer device with virtual DPCD.
3. Virtual DP-to-HDMI Protocol Converter Peer Device with
Virtual DPCD.
So we should break the assumption and handle all three types.
[how]
DP-to-DP peer device will have virtual DPCD cap upstream.
Sink peer device will have virtual DPCD on the logical port.
Dp to HDMI protocol converter peer device will have virtual DPCD
on its converter port.
For DSC capable Synaptics non VGA port we workaround by enumerating
a virutal DPCD peer device on its upstream
even if it doesn't have one.
Signed-off-by: Wenjing Liu <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
Almost every function in DC that works with stream state expects that
the current state on the stream is the one that it should be writing
out. These functions are typically triggered by specifying a particular
stream update - but the actual contents of the stream update itself
are ignored, leaving it to the DM to actually update the stream state
itself.
The problem with doing this in DM is a matter of timing. On Linux
most of this is incorrectly done in atomic check, when we actually want
it to be done during atomic commit tail while access to DC is locked.
To give an example, a commit requesting to modify color management
state for DM could come in, be rejected, but still have modified
the actual system state for the stream since it's shared memory. The
next time color management gets programmed it'll use the rejected
color management info - which might not even still be around if it's
a custom transfer function.
So a reasonable place to perform this is within DC itself and this is
the model that's currently in use for surface updates. DC can even
compare the current system state to the incoming surface update to
determine update level, something that can't currnetly be done with the
framework for stream updates.
[How]
Duplicate the framework used for surface updates for stream updates
as well. Copy all the updates after checking the update type.
Signed-off-by: Nicholas Kazlauskas <[email protected]>
Reviewed-by: Harry Wentland <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[why]
when resetting pipes from 480p to dual-pipe 8k, modulo reg write for
video optimized rate updated one pipe without changing the other, causing
sync error
[how]
removed code from dcn2
Signed-off-by: Martin Leung <[email protected]>
Reviewed-by: Jun Lei <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[Why]
The output_bpp pipe parameter was assigned an incorrect value
(color depth enum), and subsequently used to overwrite
the OutputBpp parameter calculated by DML. Seems like this had no
effect except with DSC enabled, which would make DML produce
bad outputs.
[How]
Removed assignment to OutputBpp, fixed output_bpp assignment,
and properly set ForcedOutputLinkBPP instead of OutputBpp.
Also removed condition in DML that prevented forcing of
Output BPP with DSC enabled.
Signed-off-by: Ilya Bakoulin <[email protected]>
Reviewed-by: Dmytro Laktyushkin <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
[why]
VM implemenation is missing conversion from HW values in hubbub
DM not passing actual PTB during flip
[how]
add proper HW conversion from logical values
fix cases where we programmed VA even though we are in PA
plumb in PTB from DM
Signed-off-by: Jun Lei <[email protected]>
Reviewed-by: Tony Cheng <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Fixes for the following:
- Incorrect pointer type (unsigned int instead of double)
- Incorrect DSC number of slices setting
Signed-off-by: Ilya Bakoulin <[email protected]>
Reviewed-by: Dmytro Laktyushkin <[email protected]>
Acked-by: Leo Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
