Redefine the Network-on-Chip devices to more accurately describe
the interconnect topology on QTI's SDM845 platform. Each
interconnect device can communicate with different instances of the
RPMh hardware which are described as RSCs(Resource State Coordinators).
Change-Id: Icc4ad0410e98bef4a7acc786a19bb4048ae2b1a8
Add rpmh-regulator device bindings for PMIC regulator management
via the RPMh hardware block on Qualcomm Technologies, Inc. SoCs.
This is a snapshot from msm-4.19
commit e3299424fb89 ("dt-bindings: regulator: add rpmh-regulator
bindings").
Change-Id: Ic9cd30f9da854b663e73f06d516a76f79ca8ae94
Update the minimum and maximum voltage limits for PMIC regulators
on Lahaina boards to match the latest hardware guidelines.
Change-Id: I6ec65dbb5a4d6fd5829e4ce3b39cc351d78abbf8
Some interrupt controllers in a SoC, are always powered on and have a
select interrupts routed to them, so that they can wakeup the SoC from
suspend. Add wakeup-parent DT property to refer to these interrupt
controllers.
Change-Id: I3601e3a037250a77253dce281c5f503400a6dc26
In addition to configuring the PDC, additional registers that interface
the GIC have to be configured to match the GPIO type. The registers on
some QCOM SoCs are access restricted, while on other SoCs are not. They
SoCs with access restriction to these SPI registers need to be written
from the firmware using the SCM interface. Add a flag to indicate if the
register is to be written using SCM interface.
Change-Id: I89ba52ded2451071973b81c83a53964d7ec2e486
The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy Model which in turn used by EAS to take
placement decisions.
Change-Id: Ia44ffe4fcb799663c4bb47eb18f1ac79952ed12d
Add device node for the smp2p sleepstate entry and the device node for
the smp2p sleep driver to notify dsps of apps power state changes.
Change-Id: I9f413636e98d620bfab4729afc20d9783e3a24a5
Add the QMP and QMP DEBUGFS node to facilitiate communication with AOP.
The QMP driver sends messages using the AOP msgram with a mailbox like
protocol.
Change-Id: Id67ef57b2895f98a486d5ee2724205f1d6b5e41e
Add documentation for the memory-offline driver, which
supports dynamically onlining and offlining DDR memory.
Change-Id: I9821674aaed3ec25e89023e583cbfeb0775c342e
Add qcom,msm-hang-detect to device tree to enable MSM Core Hang
Detection on all cores.
Changed from 2 nodes (one for each of silver and gold) to 1 node because
that's semantically correct for the driver.
Change-Id: I10be3a765e20460f43ce4a8cb5e6580d99439f46
Add trace unit power property to ETM. This property indicates
power unit should be power on across power collapse.
Change-Id: Ia6625b2c2fb737950614ef6c0436f523af3ceed4
Add the description for a new property, qcom,retain-regs, which
can be used to specify that retention registers should be
configured to maintain their state after a GDSC is disabled
and re-enabled.
Change-Id: Ic3649de0804d47117bddff72f3713c1ab24e33b2
Add a property to specify the parent supply voltage regulator
which must be enabled during GDSC register configuration.
Change-Id: I62e3f869f8b33faca8838151876420bb08fda601
Globally distributed switch controllers (GDSCs) are used to
switch the power supplied to a particular hardware block within
a Qualcomm Technologies, Inc. SoC on and off. Add gdsc-regulator
device bindings.
Change-Id: Iae47c4fe22c19060d120ef51249b15b20160e0fe
The Always on Processor (AOP) found on Qualcomm Technologies, Inc.
SoCs supports enabling, disabling, and scaling several shared
clocks. These clocks are controlled using the QMP mailbox
protocol. Add device bindings for AOP clock controllers.
Change-Id: I1d0b6c0abad702b2bd50fd2078eedc0907b85214
Device-tree documentation for the fastrpc nodes which contain
properties and IOMMU info for the various context banks and the
CDSP loader driver node which enables loading of firmware images
and bringing the subsystem out of reset during boot-up.
Change-Id: I7b0cc98da6348751d1f0a9d8bc73108cfc901984
