After looking at a number of different logs, it appears 0x41 likely
indicates the presense of an LVDS panel following the SPWG spec
(http://www.spwg.org/)
Signed-off-by: Ben Skeggs <[email protected]>
NV40 and older cards (pre NV50) reserve a vram bo for the vga memory at
card init. This bo is then freed at card shutdown. The problem is that
the ttm bo vram manager was already freed. So a crash occurs when the
vga bo is freed. The fix is to free the vga bo prior to freeing the ttm
bo vram manager. There might be other solutions but this seemed the
simplest to me.
Signed-off-by: Jimmy Rentz <[email protected]>
Signed-off-by: Ben Skeggs <[email protected]>
Definitely not 100% correct, but, for the configurations I've seen used
it'll read back the correct clocks now.
Signed-off-by: Ben Skeggs <[email protected]>
Many of the nv50 cards have their shader and/or memory pll
disabled at some stage.
This patch addresses those cases, so that the function
returns the correct frequency.
When the shader pll is disabled, the blob reports 2*core clock
Whereas for memory, the data stored in the vbios. This action
is incorrect as some vbioses store a clock value that is less
than the refference clock of the pll.
Thus we are reporting the reff_clk as it is the frequency the
pll actually operates
v2 - Convert NV_INFO() messages to NV_DEBUG()
Provide more information in the actuall message
Signed-off-by: Emil Velikov <[email protected]>
Signed-off-by: Ben Skeggs <[email protected]>
The nouveau_wait_for_idle() call should hopefully not have been actually
necessary, we *do* wait for the channel to go idle already. If it's
an issue somehow, the chipset-specific hooks can wait for idle themselves
before taking the lock.
Signed-off-by: Ben Skeggs <[email protected]>
In the very least VPE (PMPEG and friends) also has this style of tile
region regs, lets make them just work if/when they get added.
Signed-off-by: Ben Skeggs <[email protected]>
This needs a massive cleanup, but to catch bugs from the interface changes
vs the engine code cleanup, this will be done later.
Signed-off-by: Ben Skeggs <[email protected]>
There's lots of more-or-less independant engines present on NVIDIA GPUs
these days, and we generally want to perform the same operations on them.
Implementing new ones requires hooking into lots of different places,
the aim of this work is to make this simpler and cleaner.
NV84:NV98 PCRYPT moved over as a test.
Signed-off-by: Ben Skeggs <[email protected]>
Explanation is in the commit. If anyone has an example of where this is
*not* the case, please report it!
Signed-off-by: Ben Skeggs <[email protected]>
Improves the parsing of the memory timing table on NV50-NV98revA1 chipsets.
Added stepping to drm_nouveau_private to make sure newer NV98 (105M) is
zero rather than incorrect.
Signed-off-by: Roy Spliet <[email protected]>
Signed-off-by: Ben Skeggs <[email protected]>
This patch fixes messages such as
ERROR: space required after that ','
ERROR: spaces required around that '='
Signed-off-by: Emil Velikov <[email protected]>
Signed-off-by: Francisco Jerez <[email protected]>
Fix 'ERROR: that open brace { should be on the previous line'
Fix 'ERROR: else should follow close brace }'
Signed-off-by: Emil Velikov <[email protected]>
Signed-off-by: Francisco Jerez <[email protected]>
Fix 'ERROR: trailing whitespace',
Fix 'ERROR: do not use C99 // comments'
Signed-off-by: Emil Velikov <[email protected]>
Signed-off-by: Francisco Jerez <[email protected]>
Fix 'ERROR: code indent should use tabs where possible'
Fix 'ERROR: space required before the open parenthesis ('
Signed-off-by: Emil Velikov <[email protected]>
Signed-off-by: Francisco Jerez <[email protected]>
* 'keithp/drm-intel-next' of /ssd/git/drm-next: (301 commits)
drm/i915: split PCH clock gating init
drm/i915: add Ivybridge clock gating init function
drm/i915: Update the location of the ringbuffers' HWS_PGA registers for IVB.
drm/i915: Add support for fence registers on Ivybridge.
drm/i915: Use existing function instead of open-coding fence reg clear.
drm/i915: split clock gating init into per-chipset functions
drm/i915: set IBX pch type explicitly
drm/i915: add Ivy Bridge PCI IDs and driver feature structs
drm/i915: add PantherPoint PCH ID
agp/intel: add Ivy Bridge support
drm/i915: ring support for Ivy Bridge
drm/i915: page flip support for Ivy Bridge
drm/i915: interrupt & vblank support for Ivy Bridge
drm/i915: treat Ivy Bridge watermarks like Sandy Bridge
drm/i915: manual FDI training for Ivy Bridge
drm/i915: add swizzle/tiling support for Ivy Bridge
drm/i915: Ivy Bridge has split display and pipe control
drm/i915: add IS_IVYBRIDGE macro for checks
drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later
drm/i915: split enable/disable vblank code into chipset specific functions
...
Ibex Peak and CougarPoint already require a different setting (added
here), and future chips will likely follow that precedent.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Keith Packard <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
Some of the bits have changed, including one we were setting that enables
a VGA test mode, preventing pipe B from working at all. So add a new
IVB specific function with the right bits.
Signed-off-by: Jesse Barnes <[email protected]>
Reviewed-by: Keith Packard <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
They have been moved from the ringbuffer groups to their own group it
looks like. Fixes GPU hangs on gnome startup.
Signed-off-by: Eric Anholt <[email protected]>
Reviewed-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
The registers are the same as on Sandybridge. Fixes scrambled display
in X when it does software drawing to the GTT, and scans the results
out as tiled.
Signed-off-by: Eric Anholt <[email protected]>
Reviewed-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
This is once less place to miss a new INTEL_INFO(dev)->gen update now.
Signed-off-by: Eric Anholt <[email protected]>
Reviewed-by: Jesse Barnes <[email protected]>
Signed-off-by: Keith Packard <[email protected]>
