Workaround a hardware bug in MSENC during clock enable.
Signed-off-by: Peter De Schrijver <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.
Signed-off-by: Peter De Schrijver <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.
Signed-off-by: Peter De Schrijver <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.
Signed-off-by: Peter De Schrijver <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.
Signed-off-by: Peter De Schrijver <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.
Signed-off-by: Peter De Schrijver <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.
The following changes were done:
* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()
* Split _tegra_clk_register_pll()
Signed-off-by: Peter De Schrijver <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
tegra_boot_secondary() relies on some of the car ops. This means having an
uninitialized tegra_cpu_car_ops will lead to an early boot panic.
Providing a dummy struct avoids this and makes adding Tegra114 clock support
in a bisectable way a lot easier.
Signed-off-by: Peter De Schrijver <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
The Tegra clock driver is initialized during the ARM machine descriptor's
.init_irq() hook. It can't be initialized earlier, since dynamic memory
usage is required. It can't be initialized later, since the .init_timer()
hook needs the clocks initialized. However, at this time, udelay()
doesn't work.
The Tegra clock initialization table may enable some PLLs. Enabling a PLL
may require usage of udelay(). Hence, this can't happen right when the
clock driver is initialized.
To solve this, separate the clock driver initialization from the clock
table processing, so they can execute at separate times.
Signed-off-by: Stephen Warren <[email protected]>
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: Prashant Gaikwad <[email protected]>
[swarren: split into separate driver and device-tree patches]
Signed-off-by: Stephen Warren <[email protected]>
By default these clocks are children of pll_m, but in downstream kernels
they are reparented to pll_c. While at it, decrease their frequencies to
300 MHz because the defaults aren't in the specified range.
gr2d can reportedly run at much higher frequencies, but 300 MHz works
and is a more conservative default.
Signed-off-by: Thierry Reding <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Acked-By: Peter De Schrijver <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
The tegra_periph_reset_assert() and tegra_periph_reset_deassert()
functions can be used by drivers to reset peripherals. In order to allow
such drivers to be built as modules, export the functions.
Note that this restores the status quo as the functions were exported
before the move to the drivers/clk tree.
Signed-off-by: Thierry Reding <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
The parameter name should be "gate", not "periph". This worked, however,
because it happens that everywhere periph_clk_to_bit is called, "gate" was
in the local scope.
Signed-off-by: Yen Lin <[email protected]>
Signed-off-by: Andrew Chew <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Reviewed-by: Prashant Gaikwad <[email protected]>
Acked-by: Peter De Schrijver <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
Remove all xilinx specific names from the driver
because this is generic driver for cadence ttc.
xttc->ttc
ttcps->ttc
...
No functional changes in this driver.
Signed-off-by: Michal Simek <[email protected]>
Use cdns,ttc because this driver is Cadence Rev06
Triple Timer Counter and everybody can use it
without xilinx specific function name or probing.
Also use standard dt description for timer
and also prepare for moving to clocksource
initialization.
Signed-off-by: Michal Simek <[email protected]>
Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi.
Register it to common clock framework.
Signed-off-by: Leela Krishna Amudala <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
This patch extends suspend/resume support for SoC-specific registers to
handle differences in register sets on particular SoCs.
Signed-off-by: Tomasz Figa <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Reviewed-by: Thomas Abraham <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
This patch adds missing clock control registers to the list of registers
that should be saved across system suspend.
Signed-off-by: Tomasz Figa <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Reviewed-by: Thomas Abraham <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
This definition is specific for Exynos4210 (which has another location
than the same register on Exynos4x12 SoCs) and so needs appropriate
prefix.
Signed-off-by: Tomasz Figa <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Reviewed-by: Thomas Abraham <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
This patch adds E4210 prefix to all registers related to LCD1 clock
domain, because they are present only on Exynos4210.
Signed-off-by: Tomasz Figa <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Reviewed-by: Thomas Abraham <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
Current clock save list is shared for all Exynos4 SoCs, so it must
contain only registers present in all supported SoCs, because accessing
unavailable registers might have undefined effect.
This patch removes registers specific for particular SoCs from shared
save list, as they should be supported by separate SoC-specific lists.
Signed-off-by: Tomasz Figa <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Reviewed-by: Thomas Abraham <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
There are definitions of SRC_MASK_PERIL0 and SRC_MASK_PERIL1 registers,
but they are not used for clock definitions. This patch modifies related
clock definitions to use defined macros instead of numeric offsets.
Signed-off-by: Tomasz Figa <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Reviewed-by: Thomas Abraham <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
This patch adds preprocessor definitions of EPLL and VPLL registers and
replaces all occurences of offsets of related registers with new
definitions.
Signed-off-by: Tomasz Figa <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Reviewed-by: Thomas Abraham <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
Unimplemented clock operations should be simply omitted instead of returning
error values.
This patch removes unimplemented PLL operations to fix problems caused
by returning error code in round_rate callback.
Signed-off-by: Tomasz Figa <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Reviewed-by: Thomas Abraham <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
This patch exports clocks used by Exynos cpufreq drivers to allow lookup
using device tree. (Support to cpufreq drivers will be added in further
patches.)
Signed-off-by: Lukasz Majewski <[email protected]>
Signed-off-by: Tomasz Figa <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Reviewed-by: Thomas Abraham <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of
sclk_mpll as one of their parents.
This patch moves such clocks from common array into SoC-specific arrays
and adjusts their parent lists respectively.
Signed-off-by: Tomasz Figa <[email protected]>
Signed-off-by: Kyungmin Park <[email protected]>
Reviewed-by: Thomas Abraham <[email protected]>
Acked-by: Mike Turquette <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
The CLOCKSOURCE_OF_DECLARE lines were added without a semicolon at the
end. On my system this causes a compile-time error that looks like:
drivers/clocksource/exynos_mct.c:557:202: warning: comparison of distinct pointer types lacks a cast [enabled by default]
drivers/clocksource/exynos_mct.c:558:1: error: expected ',' or ';' before 'static'
The error didn't show up till now because there was an extra semicolon
at end of the CLOCKSOURCE_OF_DECLARE definition that was removed by
Arnd Bergmann in "clocksource: make CLOCKSOURCE_OF_DECLARE type safe"
Signed-off-by: Doug Anderson <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
Add the necessary code to initialize the interrupt controller
thru devicetree data using the irqchip infrastructure.
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
Keep a pointer to the corresponding s3c_irq_data struct as irq_chip_data.
This removes the need to fetch the intc struct from the irq_domains
host_data, thus making it independent of the underlying irq_domain
structure.
Also keep the real register offset of the interrupt in the s3c_irq_data
struct to make it independent of the hwirq structure in the irq_domain
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
For dt-enabled machines we want to use a big irq_domain over all controllers
and therefore need to access not only the main controllers but the
sub-controller as well.
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
Enables post-init setting of the desired typehandler for the interrupt.
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
The list in used was from the s3c2450, a close cousin of the s3c2416.
As it's not possible to distinguish between the s3c2416 and s3c2450
the additional interrupts of the s3c2450 will only be available thru
devicetree later.
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
