#include <dt-bindings/clock/qcom,gcc-blair.h>
#include <dt-bindings/phy/qcom,blair-qmp-usb3.h>

&soc {
	/* Primary USB port related controller */
	usb0: ssusb@4e00000 {
		compatible = "qcom,dwc-usb3-msm";
		reg = <0x4e00000 0x100000>;
		reg-names = "core_base";

		iommus = <&apps_smmu 0xe0 0x0>;
		qcom,iommu-dma = "atomic";
		qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
				<&wakegic 12 IRQ_TYPE_LEVEL_HIGH>,
				<&wakegic 93 IRQ_TYPE_EDGE_RISING>,
				<&wakegic 94 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "pwr_event_irq", "ss_phy_irq",
				"dm_hs_phy_irq", "dp_hs_phy_irq";

		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
			<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
			<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
			<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
				"xo", "sleep_clk", "utmi_clk";

		resets = <&gcc GCC_USB30_PRIM_BCR>;
		reset-names = "core_reset";

		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
		dpdm-supply = <&usb2_phy0>;
		qcom,usb-charger;

		qcom,core-clk-rate = <133333333>;
		qcom,core-clk-rate-hs = <66666667>;

		interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
		interconnects = <&system_noc MASTER_USB3_0 &bimc SLAVE_EBI>,
				<&system_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
				<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>;

		qcom,interconnect-values-nom = /* NOMINAL Votes */
						<1000000 1550000>,
						<0 2400>,
						<0 40000>;
		qcom,interconnect-values-svs = /* SVS Votes */
						<240000 700000>,
						<0 2400>,
						<0 40000>;

		qcom,num-gsi-evt-buffs = <0x3>;
		qcom,pm-qos-latency = <61>;
		qcom,gsi-reg-offset =
			<0x0fc /* GSI_GENERAL_CFG */
			 0x110 /* GSI_DBL_ADDR_L */
			 0x120 /* GSI_DBL_ADDR_H */
			 0x130 /* GSI_RING_BASE_ADDR_L */
			 0x144 /* GSI_RING_BASE_ADDR_H */
			 0x1a4>; /* GSI_IF_STS */
		qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
		qcom,gsi-disable-io-coherency;

		dwc3@4e00000 {
			compatible = "snps,dwc3";
			reg = <0x4e00000 0xcd00>;
			interrupt-parent = <&intc>;
			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
			usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;
			tx-fifo-resize;
			linux,sysdev_is_parent;
			snps,disable-clk-gating;
			snps,is-utmi-l1-suspend;
			snps,usb2-gadget-lpm-disable;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;
			snps,dis_u2_susphy_quirk;
			snps,has-lpm-erratum;
			snps,hird-threshold = /bits/ 8 <0x10>;
			snps,usb3_lpm_capable;
			maximum-speed = "super-speed";
			dr_mode = "otg";
		};
	};

	/* Primary USB port related QUSB2 PHY */
	usb2_phy0: hsphy@162b000 {
		compatible = "qcom,usb-hsphy-snps-femto";
		reg = <0x162B000 0x114>,
			<0x0162A000 0x1000>;
		reg-names = "hsusb_phy_base",
			"eud_enable_reg";

		vdd-supply = <&L7A>;
		vdda18-supply = <&L10A>;
		vdda33-supply = <&L7E>;
		qcom,vdd-voltage-level = <0 880000 880000>;

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
		clock-names = "ref_clk_src";

		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
		reset-names = "phy_reset";
		qcom,param-override-seq =
			<0xa6 0x6c	/* override_x0 */
			 0x85 0x70	/* override_x1 */
			 0x16 0x74>;	/* override x2 */
	};

	/* Primary USB port related QMP USB DP Combo PHY */
	usb_qmp_dp_phy: ssphy@1630000 {
		compatible = "qcom,usb-ssphy-qmp-dp-combo";
		reg = <0x1630000 0x3000>;
		reg-names = "qmp_phy_base";
		vdd-supply = <&L18A>;
		qcom,vdd-voltage-level = <0 880000 880000>;
		core-supply = <&L4A>;
		qcom,qmp-phy-init-seq =
			/* <reg_offset, value, delay> */
			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x60 0
			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x60 0
			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11 0
			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02 0
			USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5 0
			USB3_DP_QSERDES_TXA_LANE_MODE_2 0x00 0
			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40 0
			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09 0
			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0
			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C 0
			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF 0
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F 0
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F 0
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97 0
			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B 0
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4 0
			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
			USB3_DP_QSERDES_RXA_GM_CAL 0x1F 0
			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x60 0
			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x60 0
			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11 0
			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02 0
			USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5 0
			USB3_DP_QSERDES_TXB_LANE_MODE_2 0x00 0
			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54 0
			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09 0
			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0
			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C 0
			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F 0
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF 0
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xA6 0
			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B 0
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4 0
			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
			USB3_DP_QSERDES_RXB_GM_CAL 0x1F 0
			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0
			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0
			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
			USB3_DP_PCS_RX_SIGDET_LVL 0xA9 0
			USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
			USB3_DP_PCS_EQ_CONFIG1 0x4B 0
			USB3_DP_PCS_EQ_CONFIG5 0x10 0
			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
			0xffffffff 0xffffffff 0x00>;

		qcom,qmp-phy-reg-offset =
			<USB3_DP_PCS_PCS_STATUS1
			 USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
			 USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
			 USB3_DP_PCS_POWER_DOWN_CONTROL
			 USB3_DP_PCS_SW_RESET
			 USB3_DP_PCS_START_CONTROL
			 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
			 USB3_DP_COM_POWER_DOWN_CTRL
			 USB3_DP_COM_SW_RESET
			 USB3_DP_COM_RESET_OVRD_CTRL
			 USB3_DP_COM_PHY_MODE_CTRL
			 USB3_DP_COM_TYPEC_CTRL
			 USB3_DP_PCS_CLAMP_ENABLE
			 USB3_DP_COM_TYPEC_STATUS>;

		clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
			<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
			<&rpmcc RPM_SMD_XO_CLK_SRC>,
			<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
			<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
		clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
				"ref_clk", "com_aux_clk";

		resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
			<&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
		reset-names = "global_phy_reset", "phy_reset";
	};

	usb_nop_phy: usb_nop_phy {
		compatible = "usb-nop-xceiv";
	};

	usb_audio_qmi_dev {
		compatible = "qcom,usb-audio-qmi-dev";
		iommus = <&apps_smmu 0x0af 0x0>;
		qcom,iommu-dma = "disabled";
		qcom,usb-audio-stream-id = <0xf>;
		qcom,usb-audio-intr-num = <2>;
	};
};