/* * Copyright (c) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and * only version 2 as published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ &qupv3_se0_i2c { status = "disabled"; }; &qupv3_se0_spi_pins { qupv3_se0_spi_active: qupv3_se0_spi_active { mux { pins = "gpio0", "gpio1", "gpio2"; function = "qup00"; }; config { pins = "gpio0", "gpio1", "gpio2"; drive-strength = <6>; bias-disable; }; }; qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { mux { pins = "gpio0", "gpio1", "gpio2"; function = "gpio"; }; config { pins = "gpio0", "gpio1", "gpio2"; drive-strength = <6>; bias-disable; }; }; qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active { mux { pins = "gpio3"; function = "qup00"; }; config { pins = "gpio3"; drive-strength = <6>; bias-disable; }; }; qupv3_se0_spi_cs_sleep: qupv3_se0_spi_cs_sleep { mux { pins = "gpio3"; function = "gpio"; }; config { pins = "gpio3"; drive-strength = <6>; bias-pull-up; }; }; }; &qupv3_se0_spi { status = "ok"; pinctrl-0 = <&qupv3_se0_spi_active &qupv3_se0_spi_cs_active>; pinctrl-1 = <&qupv3_se0_spi_sleep &qupv3_se0_spi_cs_sleep>; novatek@0{ compatible = "novatek,NVT-ts-spi"; reg = <0x0>; spi-max-frequency = <9600000>; /* 4800000,9600000,15000000,19200000 */ novatek,reset-gpio = <&tlmm 21 0x00>; novatek,irq-gpio = <&tlmm 22 0x2001>; novatek,def-max-resolution = <1080 2400>; novatek,swrst-n8-addr = <0x03F0FE>; novatek,spi-rd-fast-addr = <0x03F310>; novatek,report_gesture_key; novatek,panel-supplier = "auo","boe"; panel = <&dsi_nt36675_auo_video &dsi_nt36675_boe_video>; status = "ok"; }; };