/ {
	/delete-node/ cpus;
//	/delete-node/ energy-costs;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			next-level-cache = <&L2_0>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l2-cache {
				      compatible = "arm,arch-cache";
				      cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			next-level-cache = <&L2_1>;
			#cooling-cells = <2>;
			L2_1: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			next-level-cache = <&L2_2>;
			#cooling-cells = <2>;
			L2_2: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x300>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			next-level-cache = <&L2_3>;
			#cooling-cells = <2>;
			L2_3: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x400>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
			capacity-dmips-mhz = <1946>;
			dynamic-power-coefficient = <520>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			next-level-cache = <&L2_4>;
			#cooling-cells = <2>;
			L2_4: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x500>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
			capacity-dmips-mhz = <1946>;
			dynamic-power-coefficient = <520>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			next-level-cache = <&L2_5>;
			#cooling-cells = <2>;
			L2_5: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x600>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
			capacity-dmips-mhz = <1946>;
			dynamic-power-coefficient = <520>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			next-level-cache = <&L2_6>;
			#cooling-cells = <2>;
			L2_6: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x700>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
			capacity-dmips-mhz = <1964>;
			dynamic-power-coefficient = <520>;
			qcom,freq-domain = <&cpufreq_hw 2 4>;
			next-level-cache = <&L2_7>;
			#cooling-cells = <2>;
			L2_7: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&CPU7>;
				};
			};
		};
	};
};

&soc {
	qcom,cpu0-cpugrp {
		qcom,cpu4-cpu-llcc-latmon {
			qcom,core-dev-table =
				<  691200 MHZ_TO_MBPS(  300, 16) >,
				<  940800 MHZ_TO_MBPS(  466, 16) >,
				< 1228800 MHZ_TO_MBPS(  600, 16) >,
				< 1651200 MHZ_TO_MBPS(  806, 16) >;
		};

		qcom,cpu4-llcc-ddr-latmon {
			ddr4-map {
				qcom,core-dev-table =
					<  691200 MHZ_TO_MBPS( 451, 4) >,
					<  940800 MHZ_TO_MBPS( 547, 4) >,
					< 1228800 MHZ_TO_MBPS(1017, 4) >,
					< 1651200 MHZ_TO_MBPS(1555, 4) >;
			};

			ddr5-map {
				qcom,core-dev-table =
					<  691200 MHZ_TO_MBPS( 451, 4) >,
					<  940800 MHZ_TO_MBPS( 547, 4) >,
					< 1228800 MHZ_TO_MBPS( 768, 4) >,
					< 1651200 MHZ_TO_MBPS(1555, 4) >,
					< 1900800 MHZ_TO_MBPS(1708, 4) >;
			};
		};

		qcom,cpu4-computemon {
			ddr4-map {
				qcom,core-dev-table =
					<  691200 MHZ_TO_MBPS( 451, 4) >,
					< 1228800 MHZ_TO_MBPS( 547, 4) >,
					< 1516800 MHZ_TO_MBPS( 768, 4) >,
					< 1651200 MHZ_TO_MBPS(1017, 4) >,
					< 1900800 MHZ_TO_MBPS(1555, 4) >;
			};

			ddr5-map {
				qcom,core-dev-table =
					<  691200 MHZ_TO_MBPS( 451, 4) >,
					< 1228800 MHZ_TO_MBPS( 547, 4) >,
					< 1516800 MHZ_TO_MBPS( 768, 4) >,
					< 1651200 MHZ_TO_MBPS(1555, 4) >,
					< 1900800 MHZ_TO_MBPS(1708, 4) >;
			};
		};

		qcom,cpu4-llcc-computemon {
			qcom,core-dev-table =
				< 1900800 MHZ_TO_MBPS( 150, 16) >;
		};
	};

	qcom,cpu4_grp {
		qcom,cpu4-rimps-l3-latmon {
			qcom,core-dev-table =
				<  940800  556800000 >,
				< 1228800  768000000 >,
				< 1651200 1190400000 >,
				< 1900800 1401600000 >;
		};
	};
};

&cpu4_llcc_computemon {
	qcom,core-dev-table =
		< 1900800 MHZ_TO_MBPS( 150, 16) >;
};

&cpu7_computemon {
	ddr4-map {
		qcom,core-dev-table =
			< 2380800 MHZ_TO_MBPS( 451, 4) >;
	};

	ddr5-map {
		qcom,core-dev-table =
			< 2380800 MHZ_TO_MBPS( 451, 4) >;
	};
};

&cpu7_l3_computemon {
	qcom,core-dev-table =
		< 2035200  300000000 >;
};

&cpu7_qoslatmon {
	qcom,core-dev-table =
		< 2035200 1 >;

};

&cpu7_rimps_l3_latmon {
	qcom,core-dev-table =
		< 1056000  556800000 >,
		< 1324800  768000000 >,
		< 1766400 1190400000 >;
};