&soc { usb3: ssusb@8a00000 { compatible = "qcom,dwc-usb3-msm"; reg = <0x08a00000 0xf8c00>, <0x0007e000 0x400>; reg-names = "core_base", "ahb2phy_base"; #address-cells = <1>; #size-cells = <1>; ranges; interrupts-extended = <&intc GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <&wakegic 54 IRQ_TYPE_LEVEL_HIGH>, <&wakegic 49 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event_irq","ss_phy_irq", "hs_phy_irq"; USB3_GDSC-supply = <&gdsc_usb30>; qcom,lpm-to-suspend-delay-ms = <2000>; clocks = <&gcc GCC_USB30_MASTER_CLK>, <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, <&gcc GCC_USB30_MOCK_UTMI_CLK>, <&gcc GCC_USB30_SLEEP_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_USB_PHY_CFG_AHB_CLK>; clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk", "xo", "cfg_ahb_clk"; resets = <&gcc GCC_USB_30_BCR>; reset-names = "core_reset"; qcom,core-clk-rate = <120000000>; interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; interconnects = <&system_noc MASTER_USB3 &bimc SLAVE_EBI_CH0>, <&system_noc MASTER_USB3 &pc_noc SLAVE_IPA_CFG>, <&bimc MASTER_AMPSS_M0 &system_noc SLAVE_USB3>; qcom,interconnect-values-nom = /* NOMINAL Votes */ <0 680000>, <0 2400>, <0 40000>; qcom,interconnect-values-svs = /* SVS Votes */ <0 680000>, <0 2400>, <0 40000>; qcom,num-gsi-evt-buffs = <0x3>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ 0x120 /* GSI_DBL_ADDR_H */ 0x130 /* GSI_RING_BASE_ADDR_L */ 0x140 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; dwc3@8a00000 { compatible = "snps,dwc3"; reg = <0x08a00000 0xcd00>; interrupts = ; usb-phy = <&qusb_phy>, <&ssphy>; linux,sysdev_is_parent; tx-fifo-resize; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,bus-suspend-enable; snps,usb2-gadget-lpm-disable; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; xhci-imod-value = <4000>; maximum-speed = "super-speed"; dr_mode = "otg"; }; qcom,usbbam@0x8B04000 { compatible = "qcom,usb-bam-msm"; reg = <0x8b04000 0x1b000>; interrupt-parent = <&intc>; interrupts = ; qcom,usb-bam-fifo-baseaddr = <0x08604000>; qcom,usb-bam-num-pipes = <1>; qcom,disable-clk-gating; qcom,usb-bam-override-threshold = <0x4001>; qcom,usb-bam-max-mbps-highspeed = <400>; qcom,usb-bam-max-mbps-superspeed = <3600>; qcom,reset-bam-on-connect; qcom,pipe0 { label = "ssusb-qdss-in-0"; qcom,usb-bam-mem-type = <2>; qcom,dir = <1>; qcom,pipe-num = <0>; qcom,peer-bam = <0>; qcom,peer-bam-physical-address = <0x00884000>; qcom,src-bam-pipe-index = <0>; qcom,dst-bam-pipe-index = <2>; qcom,data-fifo-offset = <0x0>; qcom,data-fifo-size = <0xc00>; qcom,descriptor-fifo-offset = <0xc00>; qcom,descriptor-fifo-size = <0x400>; }; }; }; qusb_phy: qusb@79000 { compatible = "qcom,qusb2phy"; reg = <0x00079000 0x180>, <0x01841030 0x4>; reg-names = "qusb_phy_base", "ref_clk_addr"; vdd-supply = <&pmd9650_l4>; vdda18-supply = <&pmd9650_l5>; vdda33-supply = <&pmd9650_l10>; qcom,vdd-voltage-level = <0 928000 928000>; qcom,qusb-phy-init-seq = <0xf8 0x80 0xb3 0x84 0x83 0x88 0xc0 0x8c 0x30 0x08 0x79 0x0c 0x21 0x10 0x14 0x9c 0x9f 0x1c 0x00 0x18>; phy_type = "utmi"; qcom,phy-clk-scheme = "cml"; qcom,major-rev = <1>; USB3_GDSC-supply = <&gdsc_usb30>; qcom,secure-level-shifter; clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_QUSB_REF_CLK>, <&gcc GCC_USB_PHY_CFG_AHB_CLK>, <&gcc GCC_SYS_NOC_USB3_AXI_CLK>; clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", "iface_clk"; resets = <&gcc GCC_QUSB2A_PHY_BCR>; reset-names = "phy_reset"; }; ssphy: ssphy@78000 { compatible = "qcom,usb-ssphy-qmp"; reg = <0x00078000 0x9f8>, <0x01947244 0x4>; reg-names = "qmp_phy_base", "vls_clamp_reg"; qcom,qmp-phy-init-seq = <0xac 0x14 0x00 0x34 0x08 0x00 0x174 0x30 0x00 0x70 0x0f 0x00 0x19c 0x01 0x00 0x178 0x00 0x00 0x194 0x06 0x3e8 0x48 0x0f 0x00 0x3c 0x02 0x00 0xd0 0x82 0x00 0xdc 0x55 0x00 0xe0 0x55 0x00 0xe4 0x03 0x00 0x78 0x0b 0x00 0x84 0x16 0x00 0x90 0x28 0x00 0x108 0x80 0x00 0x4c 0x15 0x00 0x50 0x34 0x00 0x54 0x00 0x00 0x18c 0x00 0x00 0xcc 0x00 0x00 0x128 0x00 0x00 0x0c 0x0a 0x00 0x10 0x01 0x00 0x1c 0x31 0x00 0x20 0x01 0x00 0x14 0x00 0x00 0x18 0x00 0x00 0x24 0xde 0x00 0x28 0x07 0x00 0x41c 0x06 0x00 0x4d8 0x02 0x00 0x4dc 0x4c 0x00 0x4e0 0xb8 0x00 0x508 0x77 0x00 0x50c 0x80 0x00 0x514 0x03 0x00 0x51c 0x16 0x00 0x510 0x0c 0x00 0x268 0x45 0x00 0x2ac 0x12 0x00 0x294 0x06 0x00 0x824 0x15 0x00 0x828 0x0e 0x00 0x8c8 0x83 0x00 0x8c4 0x02 0x00 0x8cc 0x09 0x00 0x8d0 0xa2 0x00 0x8d4 0x85 0x00 0x880 0xd1 0x00 0x884 0x1f 0x00 0x888 0x47 0x00 0x864 0x1b 0x00 0x8b8 0x75 0x00 0x8bc 0x13 0x00 0x8b0 0x86 0x00 0x8a0 0x04 0x00 0x88c 0x44 0x00 0x870 0xe7 0x00 0x874 0x03 0x00 0x878 0x40 0x00 0x87c 0x00 0x00 0x9d8 0x88 0x00 0xffffffff 0xffffffff 0x00>; qcom,qmp-phy-reg-offset = <0x974 0x8d8 0x8dc 0x804 0x800 0x808>; vdd-supply = <&pmd9650_l4>; core-supply = <&pmd9650_l5>; qcom,vdd-voltage-level = <0 928000 928000>; qcom,core-voltage-level = <0 1800000 1800000>; clocks = <&gcc GCC_USB3_AUX_CLK>, <&gcc GCC_USB3_PIPE_CLK>, <&gcc GCC_USB_PHY_CFG_AHB_CLK>, <&rpmcc RPM_SMD_LN_BB_CLK>, <&gcc GCC_USB_SS_REF_CLK>; clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk", "ref_clk_src", "ref_clk"; resets = <&gcc GCC_USB3_PHY_BCR>, <&gcc GCC_USB3PHY_PHY_BCR>; reset-names = "phy_reset", "phy_phy_reset"; }; usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; };