#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sdxnightjar.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sdxnightjar.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
#include <dt-bindings/clock/qcom,apsscc-sdxlemur.h>

#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}

/ {
	model = "Qualcomm Technologies, Inc. SDXNIGHTJAR";
	compatible = "qcom,sdxnightjar";
	qcom,msm-id = <484 0x10000>;
	interrupt-parent = <&intc>;
	#address-cells = <0x1>;
	#size-cells = <0x1>;

	chosen { };

	memory {
		device_type = "memory";
		reg = <0 0>;
	};

	reserved_memory: reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		peripheral1_mem: peripheral1_region@0x87800000 {
			no-map;
			reg = <0x87800000 0x400000>;
			label = "peripheral1_mem";
		};

		peripheral2_mem: peripheral2_region@0x87d00000 {
			no-map;
			reg = <0x87d00000 0x100000>;
			label = "peripheral2_mem";
		};

		smem_mem: smem_region@0x87e80000 {
			no-map;
			reg = <0x87e80000 0xc0000>;
			label = "smem_mem";
		};

		mss_mem: mss_region@0x88000000 {
			no-map;
			reg = <0x88000000 0x6600000>;
			label = "mss_mem";
		};

		common_cma: linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x00000000 0xffffffff>;
			reusable;
			alignment = <0x400000>;
			size = <0xc00000>;
			linux,cma-default;
		};

	};

	aliases { };

	firmware: firmware {
		scm {
			compatible = "qcom,scm";
			qcom,dload-mode = <&tcsr 0x6100>;
		};

		qtee_shmbridge {
			compatible = "qcom,tee-shared-memory-bridge";
			qcom,custom-bridge-size = <256>;
		};
	};

	cpus {
		#size-cells = <0>;
		#address-cells = <1>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
	};

	soc: soc { };
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	intc: interrupt-controller@b000000 {
		compatible = "qcom,msm-qgic2";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x0b000000 0x1000>,
		      <0x0b002000 0x1000>;
	};

	wakegic: wake-gic {
		compatible = "qcom,mpm-gic-sdxnightjar", "qcom,mpm";
		interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
		reg = <0x601b8 0x1000>,
			<0xb011008 0x4>;  /* MSM_APCS_GCC_BASE 4K */
		reg-names = "vmpm", "ipc";
		qcom,num-mpm-irqs = <96>;
		interrupt-controller;
		interrupt-parent = <&intc>;
		#interrupt-cells = <2>;
	};

	system_pm_rpm {
		compatible = "qcom,system-pm-rpm";
	};

	qcom,mpm2-sleep-counter@4a3000 {
		compatible = "qcom,mpm2-sleep-counter";
		reg = <0x004a3000 0x1000>;
		clock-frequency = <32768>;
	};

	qcom,msm-imem@8600000 {
		compatible = "qcom,msm-imem";
		reg = <0x8600000 0x1000>; /* Address and size of IMEM */
		ranges = <0x0 0x8600000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 0x8>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 0x4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 0x20>;
		};

		pil@94c {
			compatible = "qcom,msm-imem-pil";
			reg = <0x94c 0xc8>;
		};
	};

	mss: qcom,mss@4080000{
		compatible = "qcom,pil-q6v55-mss";
		reg = <0x4080000 0x100>,
		      <0x194e000 0x400>,
		      <0x4180000 0x040>,
		      <0x1810000 0x004>;
		reg-names = "qdsp6_base", "halt_base", "rmb_base",
			    "restart_reg";

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
			 <&gcc GCC_MSS_CFG_AHB_CLK>,
			 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK >,
			 <&gcc GCC_BOOT_ROM_AHB_CLK>,
			 <&gcc GCC_MSS_GPLL0_CLK_SRC>,
			 <&rpmcc RPM_SMD_QPIC_CLK>;

		clock-names = "xo", "iface_clk", "bus_clk", "mem_clk",
			      "gpll0_mss_clk", "qpic";
		qcom,proxy-clock-names = "xo";
		qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
					"gpll0_mss_clk";

		vdd_cx-supply = <&pmd9650_s5_level>;
		interrupts = <0 24 1>;
		vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
		vdd_mx-supply = <&pmd9650_l9_level>;
		vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
		vdd_pll-supply = <&pmd9650_l5>;
		qcom,vdd_pll = <1800000>;
		qcom,firmware-name = "modem";
		qcom,pil-self-auth;
		qcom,sysmon-id = <0>;
		qcom,ssctl-instance-id = <0x22>;
		qcom,override-acc;
		qcom,qdsp6v61-1-1;
		memory-region = <&mss_mem>;
		qcom,reset-clk;
		qcom,sequential-fw-load;

		interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
				<&modem_smp2p_in 0 0>,
				<&modem_smp2p_in 2 0>,
				<&modem_smp2p_in 1 0>,
				<&modem_smp2p_in 3 0>,
				<&modem_smp2p_in 7 0>;

		interrupt-names = "qcom,wdog",
				"qcom,err-fatal",
				"qcom,proxy-unvote",
				"qcom,err-ready",
				"qcom,stop-ack",
				"qcom,shutdown-ack";

		qcom,smem-states = <&modem_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";

		status = "ok";
	};

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			clock-frequency = <38400000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			clock-frequency = <32764>;
			clock-output-names = "chip_sleep_clk";
			#clock-cells = <0>;
		};
	};

	rpmcc: qcom,rpmcc {
		compatible = "qcom,rpmcc-sdxnightjar";
		#clock-cells = <1>;
	};

	gcc: qcom,gcc@1800000 {
		compatible = "qcom,sdxnightjar-gcc", "syscon";
		reg = <0x1800000 0x80000>;
		reg-names = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
			<&rpmcc RPM_SMD_XO_A_CLK_SRC>;
		clock-names = "bi_tcxo", "bi_tcxo_ao";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	cpucc: syscon@b01101c {
		compatible = "syscon";
		reg = <0xb01101c 0x4>;
	};

	debugcc: qcom,cc-debug@1874000 {
		compatible = "qcom,sdxnightjar-debugcc";
		qcom,gcc = <&gcc>;
		qcom,cpucc = <&cpucc>;
		clock-names = "xo_clk_src";
		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
		#clock-cells = <1>;
	};

	gdsc_usb30: qcom,gdsc@fc401e84 {
		compatible = "qcom,gdsc";
		regulator-name = "gdsc_usb30";
		reg = <0x185e078 0x4>;
	};

	gdsc_pcie: qcom,gdsc@0xfc401e18 {
		compatible = "qcom,gdsc";
		regulator-name = "gdsc_pcie";
		reg = <0x0185d044 0x4>;
	};

	 apsscc: clock-controller@b010008 {
		compatible = "qcom,sdxnightjar-apsscc";
		clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
			<&gcc GPLL0_AO>;
		clock-names = "bi_tcxo_ao", "gpll0_out_even";
		reg = <0xb010008 0x8>, <0xb008018 0x28>;
		reg-names = "apcs_cmd", "apcs_pll";
		vdd-pll-supply = <&VDD_CX_LEVEL_AO>;
		cpu-vdd-supply = <&VDD_CX_LEVEL_AO>;
		qcom,speed0-bin-v0 =
			<           0 RPM_SMD_REGULATOR_LEVEL_NONE>,
			<   200000000 RPM_SMD_REGULATOR_LEVEL_LOW_SVS>,
			<   384000000 RPM_SMD_REGULATOR_LEVEL_SVS>,
			<   787200000 RPM_SMD_REGULATOR_LEVEL_NOM>,
			<  1286400000 RPM_SMD_REGULATOR_LEVEL_TURBO>;
		#clock-cells = <1>;
	};

	qcom,msm-cpufreq {
		compatible = "qcom,msm-cpufreq";
		clocks = <&apsscc APCS_MUX_CLK>;
		clock-names = "cpu0_clk";
		qcom,cpufreq-table =
			<  200000 >,
			<  300000 >,
			<  384000 >,
			<  600000 >,
			<  787200 >,
			<  998400 >,
			< 1190400 >,
			< 1286400 >;
	};

	ahb_bw_opp_table: ahb-bw-opp-table {
		compatible = "operating-points-v2";
		BW_OPP_ENTRY(  19, 8); /*  144 MB/s */
		BW_OPP_ENTRY(  50, 8); /*  381 MB/s */
		BW_OPP_ENTRY(  100, 8); /* 762 MB/s */
		BW_OPP_ENTRY(  133, 8); /* 1014 MB/s */
	};

	ahb_clk: qcom,ahb-clk-src {
		compatible = "devfreq-simple-dev";
		clocks = <&gcc APSS_AHB_CLK_SRC>;
		clock-names = "devfreq_clk";
		governor = "powersave";
		qcom,bus-width = <8>;
		operating-points-v2 = <&ahb_bw_opp_table>;
	};

	cpubw: qcom,cpubw {
		compatible = "qcom,devfreq-icc";
		governor = "cpufreq";
		interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI_CH0>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	ddr_bw_opp_table: ddr-bw-opp-table {
		compatible = "operating-points-v2";
		BW_OPP_ENTRY(  202, 8); /*  1541 MB/s */
		BW_OPP_ENTRY(  404, 8); /*  3082 MB/s */
		BW_OPP_ENTRY(  518, 8); /*  3952 MB/s */
	};

	devfreq-cpufreq {
		cpubw-cpufreq {
			target-dev = <&cpubw>;
			cpu-to-dev-map =
				<  600000 1541 >,
				<  787200 3082 >,
				< 1286400 3952 >;
		};

		cpuahb-cpufreq {
			target-dev = <&ahb_clk>;
			cpu-to-dev-map =
				<  200000  144 >,
				<  384000  381 >,
				<  787200  762 >,
				<  1286400 1014 >;
		};
	};

	restart@4ab000 {
		compatible = "qcom,pshold";
		reg = <0x4ab000 0x4>,
		      <0x0193d100 0x4>;
		reg-names = "pshold-base", "tcsr-boot-misc-detect";
	};

	timer@b020000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0xb020000 0x1000>;
		clock-frequency = <19200000>;

		frame@b021000 {
			frame-number = <0>;
			interrupts = <0 7 0x4>,
				     <0 6 0x4>;
			reg = <0xb021000 0x1000>,
			      <0xb022000 0x1000>;
		};

		frame@b023000 {
			frame-number = <1>;
			interrupts = <0 8 0x4>;
			reg = <0xb023000 0x1000>;
			status = "disabled";
		};

		frame@b024000 {
			frame-number = <2>;
			interrupts = <0 9 0x4>;
			reg = <0xb024000 0x1000>;
			status = "disabled";
		};

		frame@b025000 {
			frame-number = <3>;
			interrupts = <0 10 0x4>;
			reg = <0xb025000 0x1000>;
			status = "disabled";
		};

		frame@b026000 {
			frame-number = <4>;
			interrupts = <0 11 0x4>;
			reg = <0xb026000 0x1000>;
			status = "disabled";
		};

		frame@b027000 {
			frame-number = <5>;
			interrupts = <0 12 0x4>;
			reg = <0xb027000 0x1000>;
			status = "disabled";
		};

		frame@b028000 {
			frame-number = <6>;
			interrupts = <0 13 0x4>;
			reg = <0xb028000 0x1000>;
			status = "disabled";
		};

		frame@b029000 {
			frame-number = <7>;
			interrupts = <0 14 0x4>;
			reg = <0xb029000 0x1000>;
			status = "disabled";
		};
	};

	mem_dump {
		compatible = "qcom,mem-dump";
		memory-region = <&common_cma>;

		c0_context {
			qcom,dump-size = <0x800>;
			qcom,dump-id = <0x0>;
		};

		etr_reg {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x100>;
		};

		tmc_etf {
			qcom,dump-size = <0x2000>;
			qcom,dump-id = <0xf0>;
		};

		etf_reg {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x101>;
		};

		dbgui_reg  {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0xe5>;
		};

		etm_reg {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0xa0>;
		};

		log_buf {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x110>;
		};

		log_idx {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x111>;
		};

		misc_data {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0xe8>;
		};

		pmic_data {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0xe4>;
		};

		vsense_data {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0xe9>;
		};

		rpm_data {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0xea>;
		};
	};

	qcom,sps {
		compatible = "qcom,msm-sps-4k";
		qcom,pipe-attr-ee;
	};

	qcom-secure-buffer {
		compatible = "qcom,secure-buffer";
	};

	qcom,msm_gsi {
		compatible = "qcom,msm_gsi";
	};

	qcom_rng: qrng@e3000 {
		compatible = "qcom,msm-rng";
		reg = <0xe3000 0x1000>;
		qcom,msm-rng-iface-clk;
		qcom,no-qrng-config;
		qcom,msm-bus,name = "msm-rng-noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
				<1 618 0 0>,		/* No vote */
				<1 618 0 800>;		/* 100 MB/s */
		/*TODO: Fix the clock when tree is available*/
		clock-names = "iface_clk";
	};

	qcom_tzlog: tz-log@08600720 {
		compatible = "qcom,tz-log";
		reg = <0x08600720 0x2000>;
	};

	qcom,qcedev@720000 {
		compatible = "qcom,qcedev";
		reg = <0x720000 0x20000>,
			<0x704000 0x20000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bam-pipe-pair = <1>;
		qcom,ce-hw-instance = <0>;
		qcom,ce-device = <0>;
		qcom,ce-hw-shared;
		qcom,msm-bus,name = "qcedev-noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<47 512 0 0>,
			<47 512 393600 393600>;
		/*TODO: Fix the clock when tree is available*/
		clock-names = "core_clk", "iface_clk",
			"bus_clk","core_clk_src";
		qcom,ce-opp-freq = <171430000>;
	};

	qcom,qcrypto@720000 {
		compatible = "qcom,qcrypto";
		reg = <0x720000 0x20000>,
			<0x704000 0x20000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bam-pipe-pair = <2>;
		qcom,ce-hw-instance = <0>;
		qcom,ce-device = <0>;
		qcom,ce-hw-shared;
		qcom,msm-bus,name = "qcrypto-noc";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<47 512 0 0>,
			<47 512 393600 393600>;
		/*TODO: Fix the clock when tree is available*/
		clock-names = "core_clk", "iface_clk",
			"bus_clk","core_clk_src";
		qcom,use-sw-aes-cbc-ecb-ctr-algo;
		qcom,use-sw-aes-xts-algo;
		qcom,use-sw-aes-ccm-algo;
		qcom,use-sw-ahash-algo;
		qcom,use-sw-hmac-algo;
		qcom,use-sw-aead-algo;
		qcom,ce-opp-freq = <171430000>;
	};

	qcom_seecom: qseecom@87800000 {
		compatible = "qcom,qseecom";
		reg = <0x87800000 0x200000>;
		reg-names = "secapp-region";
		memory-region = <&common_cma>;
		qcom,hlos-num-ce-hw-instances = <1>;
		qcom,hlos-ce-hw-instance = <0>;
		qcom,qsee-ce-hw-instance = <0>;
		qcom,qsee-reentrancy-support = <2>;
		qcom,support-bus-scaling;
		interconnect-names = "data_path";
		interconnects = <&pc_noc MASTER_CRYPTO_CORE_0 &bimc SLAVE_EBI_CH0>;
		/*TODO: Fix the clock when tree is available*/
		clock-names = "core_clk", "iface_clk",
			"bus_clk","core_clk_src";
		clocks =
			<&rpmcc RPM_SMD_CE1_CLK>,
			<&rpmcc RPM_SMD_CE1_CLK>,
			<&rpmcc RPM_SMD_CE1_CLK>,
			<&rpmcc RPM_SMD_CE1_CLK>;
		qcom,ce-opp-freq = <100000000>;
	};

	qcom,rmnet-ipa {
		compatible = "qcom,rmnet-ipa3";
		qcom,rmnet-ipa-ssr;
	};

	blsp1_uart1: serial@78af000 {
		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
		reg = <0x78af000 0x200>;
		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
			 <&gcc  GCC_BLSP1_AHB_CLK>;
		clock-names = "core", "iface";
		status = "disabled";
	};

	blsp1_uart2: serial@78b0000 {
		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
		reg = <0x78b0000 0x200>;
		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&gcc  GCC_BLSP1_UART2_APPS_CLK>,
			 <&gcc  GCC_BLSP1_AHB_CLK>;
		clock-names = "core", "iface";
		status = "disabled";
	};

	blsp1_uart3: serial@78b1000 {
		compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
		reg = <0x78b1000 0x200>;
		interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&gcc  GCC_BLSP1_UART3_APPS_CLK>,
			 <&gcc  GCC_BLSP1_AHB_CLK>;
		clock-names = "core", "iface";
		status = "disabled";
	};

	rpm_bus: qcom,rpm-smd {
		compatible = "qcom,rpm-smd";
		rpm-channel-name = "rpm_requests";
		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
		rpm-channel-type = <15>; /* SMD_APPS_RPM */
	};

	qcom,wdt@b017000 {
		compatible = "qcom,msm-watchdog";
		reg = <0xb017000 0x1000>;
		reg-names = "wdt-base";
		interrupts = <1 3 IRQ_TYPE_EDGE_RISING>,
			<1 2 IRQ_TYPE_EDGE_RISING>;
		qcom,bark-time = <11000>;
		qcom,pet-time = <10000>;
	};

	qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>;
	};

	jtag_mm0: jtagmm@842000 {
		compatible = "qcom,jtag-mm";
		reg = <0x842000 0x1000>,
		      <0x840000 0x1000>;
		reg-names = "etm-base","debug-base";

		qcom,coresight-jtagmm-cpu = <&CPU0>;
		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	tcsr_mutex_regs: syscon@1905000 {
		compatible = "syscon";
		reg = <0x1905000 0x20000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_regs 0 0x1000>;
		#hwlock-cells = <1>;
	};

	tcsr: syscon@0x1937000 {
		compatible = "syscon";
		reg = <0x1937000 0x21000>;
	};

	apcs_glb: mailbox@0xb011008 {
		compatible = "qcom,sdxnightjar-apcs-gcc";
		reg = <0xb011008 0x4>;
		#mbox-cells = <1>;
	};

	rpm_msg_ram: memory@60000 {
		compatible = "qcom,rpm-msg-ram";
		reg = <0x60000 0x6000>;
	};

	qcom,ipc-spinlock@1905000 {
		compatible = "qcom,ipc-spinlock-sfpb";
		reg = <0x1905000 0x8000>;
		qcom,num-locks = <8>;
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;
		hwlocks = <&tcsr_mutex 3>;
	};

	qcom,smd {
		compatible = "qcom,smd";

		modem {
			qcom,smd-edge = <0>;
			mboxes = <&apcs_glb 12>;
			qcom,remote-pid = <1>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
			label = "mpss";

			qcom,smd-channels = "IPCRTR";
			qcom,modem_qrtr {
				qcom,low-latency;
			};
		};

		rpm {
			qcom,smd-edge = <15>;
			mboxes = <&apcs_glb 0>;
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			label = "rpm";

			rpm_requests: rpm_requests@0 {
				compatible = "qcom,rpm-smd";
				qcom,smd-channels = "rpm_requests";
			};
		};
	};

	qcom,glink {
		compatible = "qcom,glink";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		glink_modem: modem {
			qcom,remote-pid = <1>;
			transport = "smem";
			mboxes = <&apcs_glb 15>;
			mbox-names = "mpss_smem";
			interrupts = <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>;

			label = "modem";
			qcom,glink-label = "mpss";

			qcom,modem_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};
		};
	};

	qcom,glinkpkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-at-mdm0 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DS";
			qcom,glinkpkt-dev-name = "at_mdm0";
		};

		qcom,glinkpkt-data5-cntl {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA5_CNTL";
			qcom,glinkpkt-dev-name = "smdcntl0";
		};

		qcom,glinkpkt-data6-cntl {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA6_CNTL";
			qcom,glinkpkt-dev-name = "smdcntl1";
		};

		qcom,glinkpkt-data40-cntl {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA40_CNTL";
			qcom,glinkpkt-dev-name = "smdcntl8";
		};

		qcom,glinkpkt-data1 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA1";
			qcom,glinkpkt-dev-name = "smd7";
		};

		qcom,glinkpkt-data4 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA4";
			qcom,glinkpkt-dev-name = "smd8";
		};

		qcom,glinkpkt-data11 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA11";
			qcom,glinkpkt-dev-name = "smd11";
		};

		qcom,glinkpkt-data21 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA21";
			qcom,glinkpkt-dev-name = "smd21";
		};

		qcom,glinkpkt-data22 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA22";
			qcom,glinkpkt-dev-name = "smd22";
		};
	};

	qcom,smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
		mboxes = <&apcs_glb 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		/* ipa - inbound entry from mss */
		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

	};

	qnand_1: nand@7980000 {
		compatible = "qcom,msm-nand";
		reg = <0x07980000 0x1000>,
			<0x07984000 0x1a000>;
		reg-names = "nand_phys",
			"bam_phys";
		qcom,reg-adjustment-offset = <0x4000>;

		interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "bam_irq";

		clock-names = "core_clk";
		clocks = <&rpmcc RPM_SMD_QPIC_CLK>;

		interconnects = <&pc_noc MASTER_QPIC &bimc SLAVE_EBI_CH0>;
		interconnect-names = "nand-ddr";
		qcom,msm-bus,name = "qpic_nand";
		qcom,msm-bus,num-cases = <2>;
		qcom,msm-bus,num-paths = <1>;
		qcom,msm-bus,vectors-KBps =
			<0 0>,
		/* Voting for max b/w on PNOC bus for now */
			<400000 400000>;

		status = "disabled";
	};

	sdhc_1: sdhci@7824000 {
		compatible = "qcom,sdhci-msm-v4";
		reg = <0x07824900 0x500>, <0x07824000 0x800>;
		reg-names = "hc_mem", "core_mem";

		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		qcom,devfreq,freq-table = <50000000 200000000>;

		interconnects = <&pc_noc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>;
		interconnect-names = "sdhc-ddr";
		qcom,msm-bus,name = "sdhc1";
		qcom,msm-bus,num-cases = <7>;
		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps = <0 0>, /* No vote */
				<1600 3200>,    /* 400 KB/s*/
				<100000 200000>, /* 25 MB/s */
				<200000 400000>, /* 50 MB/s */
				<400000 800000>, /* 100 MB/s */
				<400000 800000>, /* 200 MB/s */
				<2048000 4096000>; /* Max. bandwidth */
		qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
			100000000 200000000 4294967295>;

		clocks = <&gcc GCC_SDCC1_AHB_CLK>,
			 <&gcc GCC_SDCC1_APPS_CLK>;
		clock-names = "iface", "core";

		bus-width = <4>;

		status = "disabled";

		qos0 {
			mask = <0x1>;
			vote = <70>;
		};
	};

	thermal_zones: thermal-zones {};

	spmi_bus: qcom,spmi@200f000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0x200f000 0x1000>,
			<0x2400000 0x800000>,
			<0x2c00000 0x800000>,
			<0x3800000 0x200000>,
			<0x200a000 0x2100>; /* includes SPMI_CFG and GENI_CFG */
		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
		interrupt-names = "periph_irq";
		interrupts-extended = <&wakegic 88 IRQ_TYPE_LEVEL_HIGH>;
		qcom,channel = <0>;
		qcom,ee = <0>;
		#interrupt-cells = <4>;
		interrupt-controller;
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
	};

	bimc: interconnect@400000 {
		reg = <0x400000 0x62000>;
		compatible = "qcom,sdxnightjar-bimc";
		qcom,util-factor = <153>;
		qcom,keepalive;
		#interconnect-cells = <1>;
		clock-names = "bus", "bus_a";
		clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
			<&rpmcc RPM_SMD_BIMC_A_CLK>;
	};

	pc_noc: interconnect@500000 {
		reg = <0x500000 0x11000>;
		compatible = "qcom,sdxnightjar-pcnoc";
		qcom,keepalive;
		#interconnect-cells = <1>;
		clock-names = "bus", "bus_a";
		clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
			<&rpmcc RPM_SMD_PCNOC_A_CLK>;
	};

	system_noc: interconnect@580000 {
		reg = <0x580000 0x14000>;
		compatible = "qcom,sdxnightjar-snoc";
		qcom,keepalive;
		#interconnect-cells = <1>;
		clock-names = "bus", "bus_a";
		clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
			<&rpmcc RPM_SMD_SNOC_A_CLK>;
	};

	qcom,msm_gsi {
		compatible = "qcom,msm_gsi";
	};

	qcom,rmnet-ipa {
		compatible = "qcom,rmnet-ipa3";
		qcom,rmnet-ipa-ssr;
	};

	ipa_hw: qcom,ipa@07B00000 {
		compatible = "qcom,ipa";
		reg = <0x07B00000 0x34000>,
			<0x07B84000 0x31FFFF>,
			<0x07B04000 0x2C000>;
		reg-names = "ipa-base", "bam-base", "gsi-base";
		interrupts =
			<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "ipa-irq", "bam-irq", "gsi-irq";
		qcom,ipa-hw-ver = <10>; /* IPA core version = IPAv3.0 */
		qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */
		qcom,platform-type = <0>; /* MDM platform */
		qcom,ee = <0>;
		qcom,use-rg10-limitation-mitigation;
		qcom,use-wrapper-pm-support;
		qcom,use-ipa-tethering-bridge;
		qcom,modem-cfg-emb-pipe-flt;
		clock-names = "core_clk";
		clocks = <&rpmcc RPM_SMD_IPA_CLK>;
		qcom,interconnect,num-cases = <5>;
		qcom,interconnect,num-paths = <3>;
		interconnects = <&system_noc MASTER_IPA &bimc SLAVE_EBI_CH0>,
				<&system_noc MASTER_IPA &system_noc SLAVE_OCIMEM>,
				<&bimc MASTER_AMPSS_M0 &pc_noc SLAVE_IPA_CFG>;
		interconnect-names = "ipa_to_ebi1", "ipa_to_imem", "appss_to_ipa";
		/* No vote */
		qcom,no-vote =
			<0 0 0 0 0 0>;
		/* SVS2 */
		qcom,svs2 =
			<80000 64000 80000 64000 80000 16000>;
		/* SVS */
		qcom,svs =
			<80000 640000 80000 640000 80000 160000>;
		/* NOMINAL */
		qcom,nominal =
			<206000 960000 206000 960000 206000 400000>;
		/* TURBO */
		qcom,turbo =
			<206000 3600000 206000 3600000 206000 960000>;
		qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";

		qcom,throughput-threshold = <310 600 1000>;
		qcom,scaling-exceptions = <>;

		/* ipa tz unlock registers */
		qcom,ipa-tz-unlock-reg =
			<0x4043583c 0x1000>; /* 32-bit reg addr and size */
		/* smp2p gpio information */
		qcom,smp2p_map_ipa_1_out {
			compatible = "qcom,smp2p-map-ipa-1-out";
			qcom,smem-states = <&smp2p_ipa_1_out 0>;
			qcom,smem-state-names = "ipa-smp2p-out";
		};

		qcom,smp2p_map_ipa_1_in {
			compatible = "qcom,smp2p-map-ipa-1-in";
			interrupts-extended = <&smp2p_ipa_1_in 0 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ipa-smp2p-in";
		};
	};
};

#include "pmd9650.dtsi"
#include "pmd9650-rpm-regulator.dtsi"
#include "sdxnightjar-regulator.dtsi"
#include "sdxnightjar-usb.dtsi"
#include "sdxnightjar-coresight.dtsi"
#include "sdxnightjar-pinctrl.dtsi"
#include "sdxnightjar-ion.dtsi"
#include "sdxnightjar-pm.dtsi"
#include "sdxnightjar-blsp.dtsi"
#include "sdxnightjar-cnss.dtsi"
#include "sdxnightjar-pcie.dtsi"
#include "sdxnightjar-audio.dtsi"
#include "sdxnightjar-audio-overlay.dtsi"
#include "sdxnightjar-thermal.dtsi"

&pmd9650_gpios {
	ambient_therm {
		ambient_therm_default: ambient_therm_default {
			pins = "gpio2";
			bias-high-impedance;
		};
	};
};

&pmd9650_vadc {
	case_therm {
		reg = <ADC5_AMUX_THM1_100K_PU>;
		label = "case_therm";
		qcom,ratiometric;
		qcom,hw-settle-time = <200>;
		qcom,pre-scaling = <1 1>;
	};

	pa_therm1 {
		reg = <ADC5_AMUX_THM2_100K_PU>;
		label = "pa_therm1";
		qcom,ratiometric;
		qcom,hw-settle-time = <200>;
		qcom,pre-scaling = <1 1>;
	};

	pa_therm2 {
		reg = <ADC5_AMUX_THM3_100K_PU>;
		label = "pa_therm2";
		qcom,ratiometric;
		qcom,hw-settle-time = <200>;
		qcom,pre-scaling = <1 1>;
	};

	ambient_therm {
		reg = <ADC5_GPIO2_100K_PU>;
		label = "ambient_therm";
		qcom,ratiometric;
		qcom,hw-settle-time = <200>;
		qcom,pre-scaling = <1 1>;
	};
};

&spmi_bus {
	qcom,pmd9650@0 {
		pmd9650_adc_tm_iio: adc_tm@3400 {
			compatible = "qcom,adc-tm5-iio";
			reg = <0x3400>;
			#thermal-sensor-cells = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			io-channels = <&pmd9650_vadc ADC5_XO_THERM_100K_PU>,
					<&pmd9650_vadc ADC5_AMUX_THM1_100K_PU>,
					<&pmd9650_vadc ADC5_AMUX_THM2_100K_PU>,
					<&pmd9650_vadc ADC5_AMUX_THM3_100K_PU>,
					<&pmd9650_vadc ADC5_GPIO2_100K_PU>;

			xo_therm {
				reg = <ADC5_XO_THERM_100K_PU>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
			};

			case_therm {
				reg = <ADC5_AMUX_THM1_100K_PU>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
			};

			pa_therm1 {
				reg = <ADC5_AMUX_THM2_100K_PU>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
			};

			pa_therm2 {
				reg = <ADC5_AMUX_THM3_100K_PU>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
			};

			ambient_therm {
				reg = <ADC5_GPIO2_100K_PU>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
			};
		};
	};
};

&thermal_zones {
	xo-therm-usr {
		polling-delay-passive = <0>;
		polling-delay = <0>;
		thermal-governor = "user_space";
		thermal-sensors = <&pmd9650_adc_tm_iio ADC5_XO_THERM_100K_PU>;
		wake-capable-sensor;
		trips {
			active-config0 {
				temperature = <125000>;
				hysteresis = <1000>;
				type = "passive";
			};
		};
	};

	case-therm-usr {
		polling-delay-passive = <0>;
		polling-delay = <0>;
		thermal-governor = "user_space";
		thermal-sensors = <&pmd9650_adc_tm_iio ADC5_AMUX_THM1_100K_PU>;
		wake-capable-sensor;
		trips {
			active-config0 {
				temperature = <125000>;
				hysteresis = <1000>;
				type = "passive";
			};
		};
	};

	pa-therm1-usr {
		polling-delay-passive = <0>;
		polling-delay = <0>;
		thermal-governor = "user_space";
		thermal-sensors = <&pmd9650_adc_tm_iio ADC5_AMUX_THM2_100K_PU>;
		wake-capable-sensor;
		trips {
			active-config0 {
				temperature = <125000>;
				hysteresis = <1000>;
				type = "passive";
			};
		};
	};

	pa-therm2-usr {
		polling-delay-passive = <0>;
		polling-delay = <0>;
		thermal-governor = "user_space";
		thermal-sensors = <&pmd9650_adc_tm_iio ADC5_AMUX_THM3_100K_PU>;
		wake-capable-sensor;
		trips {
			active-config0 {
				temperature = <125000>;
				hysteresis = <1000>;
				type = "passive";
			};
		};
	};

	ambient-therm-usr {
		polling-delay-passive = <0>;
		polling-delay = <0>;
		thermal-governor = "user_space";
		thermal-sensors = <&pmd9650_adc_tm_iio ADC5_GPIO2_100K_PU>;
		wake-capable-sensor;
		trips {
			active-config0 {
				temperature = <125000>;
				hysteresis = <1000>;
				type = "passive";
			};
		};
	};
};

&i2c_3 {
	status = "ok";
	smb1351_otg_supply: smb1351-charger@55 {
		compatible = "qcom,smb1351-charger";
		reg = <0x55>;
		interrupt-parent = <&tlmm_pinmux>;
		interrupts = <83 IRQ_TYPE_LEVEL_LOW>;
		interrupts-extended = <&tlmm_pinmux 83 IRQ_TYPE_LEVEL_LOW>, <&pmd9650_gpios 5 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "smb1351_chg_stat_irq","smb1351_usb_id_irq";
		qcom,usb-id-gpio = <&pmd9650_gpios 5 IRQ_TYPE_LEVEL_LOW>;
		qcom,float-voltage-mv = <4200>;
		qcom,charging-timeout = <1536>;
		qcom,recharge-thresh-mv = <200>;
		qcom,iterm-ma = <100>;
		regulator-name = "smb1351_otg_supply";
		pinctrl-names = "default";
		pinctrl-0 = <&smb_stat_active>, <&usb_id_detect>;
		qcom,switch-freq = <2>;
		qcom,id-line-not-connected;
		dpdm-supply = <&qusb_phy>;
	};
};

&usb3 {
	extcon = <&smb1351_otg_supply>;
};