#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,camcc-sm6150.h>
#include <dt-bindings/clock/qcom,dispcc-sm6150.h>
#include <dt-bindings/clock/qcom,gpucc-sm6150.h>
#include <dt-bindings/clock/qcom,gcc-sm6150.h>
#include <dt-bindings/clock/qcom,scc-sm6150.h>
#include <dt-bindings/clock/qcom,videocc-sm6150.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm6150.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
				opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
				opp-supported-hw = <ddrtype>;}

/ {
	model = "Qualcomm Technologies, Inc. SM6150";
	compatible = "qcom,sm6150";
	qcom,msm-name = "SM6150";
	qcom,msm-id = <355 0x0>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;
	memory { device_type = "memory"; reg = <0 0 0 0>; };

	aliases {
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
		serial0 = &qupv3_se0_2uart;
		sdhc0 = &sdhc_1;
		sdhc1 = &sdhc_2;
		spi10 = &qupv3_se10_spi;
		hsuart0 = &qupv3_se7_4uart;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			cache-size = <0x8000>;
			next-level-cache = <&L2_0>;
			qcom,freq-domain = <&cpufreq_hw 0 6>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
				      compatible = "arm,arch-cache";
				      cache-size = <0x100000>;
				      cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			cache-size = <0x8000>;
			next-level-cache = <&L2_100>;
			qcom,freq-domain = <&cpufreq_hw 0 6>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;
			L2_100: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};


		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			cache-size = <0x8000>;
			next-level-cache = <&L2_200>;
			qcom,freq-domain = <&cpufreq_hw 0 6>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;
			L2_200: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			cache-size = <0x8000>;
			next-level-cache = <&L2_300>;
			qcom,freq-domain = <&cpufreq_hw 0 6>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;
			L2_300: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x400>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			cache-size = <0x8000>;
			next-level-cache = <&L2_400>;
			qcom,freq-domain = <&cpufreq_hw 0 6>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;
			L2_400: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x500>;
			enable-method = "psci";
			cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			cache-size = <0x8000>;
			next-level-cache = <&L2_500>;
			qcom,freq-domain = <&cpufreq_hw 0 6>;
			qcom,lmh-dcvs = <&lmh_dcvs0>;
			L2_500: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x10000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x600>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
			capacity-dmips-mhz = <1740>;
			dynamic-power-coefficient = <404>;
			cache-size = <0x10000>;
			next-level-cache = <&L2_600>;
			qcom,freq-domain = <&cpufreq_hw 1 2>;
			qcom,lmh-dcvs = <&lmh_dcvs1>;
			#cooling-cells = <2>;
			L2_600: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "arm,armv8";
			reg = <0x0 0x700>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
			capacity-dmips-mhz = <1740>;
			dynamic-power-coefficient = <404>;
			cache-size = <0x10000>;
			next-level-cache = <&L2_700>;
			qcom,freq-domain = <&cpufreq_hw 1 2>;
			qcom,lmh-dcvs = <&lmh_dcvs1>;
			L2_700: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-size = <0x40000>;
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};

				core4 {
					cpu = <&CPU4>;
				};

				core5 {
					cpu = <&CPU5>;
				};

			};

			cluster1 {
				core0 {
					cpu = <&CPU6>;
				};

				core1 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	chosen {
	};

	soc: soc { };

	firmware: firmware {
		android {
			compatible = "android,firmware";
			vbmeta {
				compatible = "android,vbmeta";
				parts = "vbmeta,boot,system,vendor,dtbo";
			};

			fstab {
				compatible = "android,fstab";
				vendor {
					compatible = "android,vendor";
					dev = "/dev/block/platform/soc
						/1d84000.ufshc/by-name/vendor";
					type = "ext4";
					mnt_flags = "ro,barrier=1,discard";
					fsmgr_flags = "wait,slotselect,avb";
					status = "ok";
				};
			};
		};
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_region: hyp_region@85700000 {
			no-map;
			reg = <0x0 0x85700000 0x0 0x600000>;
		};

		xbl_aop_mem: xbl_aop_mem@85e00000 {
			no-map;
			reg = <0x0 0x85e00000 0x0 0x120000>;
		};

		aop_cmd_db: memory@85f20000 {
			compatible = "qcom,cmd-db";
			reg = <0x0 0x85f20000 0x0 0x20000>;
			no-map;
		};

		sec_apps_mem: sec_apps_region@85fff000 {
			no-map;
			reg = <0x0 0x85fff000 0x0 0x1000>;
		};

		smem_region: smem@86000000 {
			no-map;
			reg = <0x0 0x86000000 0x0 0x200000>;
		};

		removed_region: removed_region@86200000 {
			no-map;
			reg = <0x0 0x86200000 0x0 0x2d00000>;
		};

		pil_camera_mem: camera_region@8ab00000 {
			no-map;
			reg = <0x0 0x8ab00000 0x0 0x500000>;
		};

		pil_modem_mem: modem_region@8b000000 {
			no-map;
			reg = <0x0 0x8b000000 0x0 0x8400000>;
		};

		pil_video_mem: pil_video_region@93400000 {
			no-map;
			reg = <0x0 0x93400000 0x0 0x500000>;
		};

		wlan_msa_mem: wlan_msa_region@93900000 {
			no-map;
			reg = <0x0 0x93900000 0x0 0x200000>;
		};

		pil_cdsp_mem: cdsp_regions@93b00000 {
			no-map;
			reg = <0x0 0x93b00000 0x0 0x1e00000>;
		};

		pil_adsp_mem: pil_adsp_region@95900000 {
			no-map;
			reg = <0x0 0x95900000 0x0 0x1e00000>;
		};

		pil_ipa_fw_mem: ips_fw_region@97700000 {
			no-map;
			reg = <0x0 0x97700000 0x0 0x10000>;
		};

		pil_ipa_gsi_mem: ipa_gsi_region@97710000 {
			no-map;
			reg = <0x0 0x97710000 0x0 0x5000>;
		};

		pil_gpu_mem: gpu_region@97715000 {
			no-map;
			reg = <0x0 0x97715000 0x0 0x2000>;
		};

		qseecom_mem: qseecom_region {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0x0 0x9e400000 0x0 0x1400000>;
		};

		cdsp_sec_mem: cdsp_sec_regions@9f800000 {
			no-map;
			reg = <0x0 0x9f800000 0x0 0x1e00000>;
		};

		adsp_mem: adsp_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x800000>;
		};

		sdsp_mem: sdsp_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x400000>;
		};

		user_contig_mem: user_contig_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x1000000>;
		};

		qseecom_ta_mem: qseecom_ta_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x1000000>;
		};

		sp_mem: sp_region {  /* SPSS-HLOS ION shared mem */
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x800000>;
		};

		secure_display_memory: secure_display_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x8c00000>;
		};

		cont_splash_memory: cont_splash_region@9c000000 {
			reg = <0x0 0x9c000000 0x0 0x0f00000>;
			label = "cont_splash_region";
		};

		dfps_data_memory: dfps_data_region@9cf00000 {
			reg = <0x0 0x9cf00000 0x0 0x0100000>;
			label = "dfps_data_region";
		};

		disp_rdump_memory: disp_rdump_region@9c000000 {
			reg = <0x0 0x9c000000 0x0 0x01000000>;
			label = "disp_rdump_region";
		};

		dump_mem: mem_dump_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			size = <0 0x2800000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			alloc-ranges = <0 0x00000000 0 0xffffffff>;
			reusable;
			alignment = <0 0x400000>;
			size = <0 0x2000000>;
			linux,cma-default;
		};
	};

	qcom-secure-buffer {
		compatible = "qcom,secure-buffer";
	};

};

#include "display/sm6150-sde-pll.dtsi"
#include "display/sm6150-sde.dtsi"

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	intc: interrupt-controller@17a00000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17a00000 0x10000>,     /* GICD */
		      <0x17a60000 0x100000>;    /* GICR * 8 */
		interrupts = <1 9 4>;
		interrupt-parent = <&intc>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 1 0xf08>,
			     <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 0 0xf08>;
		clock-frequency = <19200000>;
	};

	timer@17c20000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17c20000 0x1000>;
		clock-frequency = <19200000>;

		frame@17c21000 {
			frame-number = <0>;
			interrupts = <0 8 0x4>,
				     <0 6 0x4>;
			reg = <0x17c21000 0x1000>,
			      <0x17c22000 0x1000>;
		};

		frame@17c23000 {
			frame-number = <1>;
			interrupts = <0 9 0x4>;
			reg = <0x17c23000 0x1000>;
			status = "disabled";
		};

		frame@17c25000 {
			frame-number = <2>;
			interrupts = <0 10 0x4>;
			reg = <0x17c25000 0x1000>;
			status = "disabled";
		};

		frame@17c27000 {
			frame-number = <3>;
			interrupts = <0 11 0x4>;
			reg = <0x17c27000 0x1000>;
			status = "disabled";
		};

		frame@17c29000 {
			frame-number = <4>;
			interrupts = <0 12 0x4>;
			reg = <0x17c29000 0x1000>;
			status = "disabled";
		};

		frame@17c2b000 {
			frame-number = <5>;
			interrupts = <0 13 0x4>;
			reg = <0x17c2b000 0x1000>;
			status = "disabled";
		};

		frame@17c2d000 {
			frame-number = <6>;
			interrupts = <0 14 0x4>;
			reg = <0x17c2d000 0x1000>;
			status = "disabled";
		};
	};

	llcc_pmu: llcc-pmu@90cc000 {
		compatible = "qcom,llcc-pmu-ver2";
		reg = <0x090cc000 0x300>;
		reg-names = "lagg-base";
	};

	llcc_bw_opp_table: llcc-bw-opp-table {
		compatible = "operating-points-v2";
		BW_OPP_ENTRY( 150, 16); /*  2288 MB/s */
		BW_OPP_ENTRY( 300, 16); /*  4577 MB/s */
		BW_OPP_ENTRY( 466, 16); /*  7110 MB/s */
		BW_OPP_ENTRY( 600, 16); /*  9155 MB/s */
		BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
		BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
	};

	cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
		compatible = "qcom,devfreq-icc";
		governor = "performance";
		interconnects = <&gem_noc MASTER_APPSS_PROC
				&gem_noc SLAVE_LLCC>;
		qcom,active-only;
		operating-points-v2 = <&llcc_bw_opp_table>;
	};

	cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
		compatible = "qcom,bimc-bwmon4";
		reg = <0x90b6300 0x300>, <0x90b6200 0x200>;
		reg-names = "base", "global_base";
		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
		qcom,mport = <0>;
		qcom,hw-timer-hz = <19200000>;
		qcom,target-dev = <&cpu_cpu_llcc_bw>;
		qcom,count-unit = <0x10000>;
	};

	ddr_bw_opp_table: ddr-bw-opp-table {
		compatible = "operating-points-v2";
		BW_OPP_ENTRY_DDR( 200, 4, 0x80); /*  762 MB/s */
		BW_OPP_ENTRY_DDR( 300, 4, 0x80); /* 1144 MB/s */
		BW_OPP_ENTRY_DDR( 451, 4, 0x80); /* 1720 MB/s */
		BW_OPP_ENTRY_DDR( 547, 4, 0x80); /* 2086 MB/s */
		BW_OPP_ENTRY_DDR( 681, 4, 0x80); /* 2597 MB/s */
		BW_OPP_ENTRY_DDR( 768, 4, 0x80); /* 2929 MB/s */
		BW_OPP_ENTRY_DDR(1017, 4, 0x80); /* 3879 MB/s */
		BW_OPP_ENTRY_DDR(1353, 4, 0x80); /* 5161 MB/s */
		BW_OPP_ENTRY_DDR(1555, 4, 0x80); /* 5931 MB/s */
		BW_OPP_ENTRY_DDR(1804, 4, 0x80); /* 6881 MB/s */
	};

	cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
		compatible = "qcom,devfreq-icc-ddr";
		governor = "performance";
		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 {
		compatible = "qcom,bimc-bwmon5";
		reg = <0x90cd000 0x1000>;
		reg-names = "base";
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		qcom,hw-timer-hz = <19200000>;
		qcom,target-dev = <&cpu_llcc_ddr_bw>;
		qcom,count-unit = <0x10000>;
	};

	cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {
		compatible = "qcom,devfreq-icc-l3";
		reg = <0x18321110 0x500>;
		reg-names = "ftbl-base";
		qcom,ftbl-row-size = <0x20>;
		governor = "performance";
		interconnects = <&osm_l3 MASTER_OSM_L3_APPS
				&osm_l3 SLAVE_OSM_L3_CLUSTER0>;
	};

	cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {
		qcom,core-dev-table =
			<  576000  300000000 >,
			< 1017600  556800000 >,
			< 1209660  806400000 >,
			< 1516800  940800000 >,
			< 1804800 1363200000 >;
	};

	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
		compatible = "qcom,devfreq-icc";
		governor = "performance";
		interconnects = <&gem_noc MASTER_APPSS_PROC
				&gem_noc SLAVE_LLCC>;
		qcom,active-only;
		operating-points-v2 = <&llcc_bw_opp_table>;
	};

	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
		compatible = "qcom,devfreq-icc-ddr";
		governor = "performance";
		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
		compatible = "qcom,devfreq-icc-ddr";
		governor = "performance";
		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
		compatible = "qcom,arm-memlat-cpugrp";
		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

		cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
			qcom,target-dev = <&cpu0_cpu_l3_lat>;
			qcom,cachemiss-ev = <0x17>;
			qcom,stall-cycle-ev = <0xE7>;
			qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
		};

		cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,target-dev = <&cpu0_cpu_llcc_lat>;
			qcom,cachemiss-ev = <0x2A>;
			qcom,stall-cycle-ev = <0xE7>;
			qcom,core-dev-table =
				<  748000 MHZ_TO_MBPS(150, 16) >,
				< 1209600 MHZ_TO_MBPS(300, 16) >,
				< 1516800 MHZ_TO_MBPS(466, 16) >,
				< 1804800 MHZ_TO_MBPS(600, 16) >;
		};

		cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
			qcom,target-dev = <&cpu0_llcc_ddr_lat>;
			qcom,cachemiss-ev = <0x1000>;
			qcom,core-dev-table =
				<  748000 MHZ_TO_MBPS( 300, 4) >,
				< 1017600 MHZ_TO_MBPS( 451, 4) >,
				< 1209600 MHZ_TO_MBPS( 547, 4) >,
				< 1516800 MHZ_TO_MBPS( 768, 4) >,
				< 1804800 MHZ_TO_MBPS(1017, 4) >;
		};

		cpu0_computemon: qcom,cpu0-computemon {
			compatible = "qcom,arm-compute-mon";
			qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
			qcom,core-dev-table =
				<  748800 MHZ_TO_MBPS( 300, 4) >,
				< 1209600 MHZ_TO_MBPS( 451, 4) >,
				< 1593600 MHZ_TO_MBPS( 547, 4) >,
				< 1804800 MHZ_TO_MBPS( 768, 4) >;
		};
	};

	cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat {
		compatible = "qcom,devfreq-icc-l3";
		reg = <0x18321110 0x500>;
		reg-names = "ftbl-base";
		qcom,ftbl-row-size = <0x20>;
		governor = "performance";
		interconnects = <&osm_l3 MASTER_OSM_L3_APPS
				&osm_l3 SLAVE_OSM_L3_CLUSTER1>;
	};

	cpu6_cpu_l3_tbl: qcom,cpu6_cpu_l3_tbl {
		qcom,core-dev-table =
			< 1017600  556800000 >,
			< 1209600  806400000 >,
			< 1516800  940800000 >,
			< 1708800 1209600000 >,
			< 2208000 1363200000 >;
	};

	cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat {
		compatible = "qcom,devfreq-icc";
		governor = "performance";
		interconnects = <&gem_noc MASTER_APPSS_PROC
				&gem_noc SLAVE_LLCC>;
		qcom,active-only;
		operating-points-v2 = <&llcc_bw_opp_table>;
	};

	cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat {
		compatible = "qcom,devfreq-icc-ddr";
		governor = "performance";
		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {
		compatible = "qcom,devfreq-icc-ddr";
		governor = "performance";
		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
		qcom,active-only;
		operating-points-v2 = <&ddr_bw_opp_table>;
	};

	cpu6_memlat_cpugrp: qcom,cpu6-cpugrp {
		compatible = "qcom,arm-memlat-cpugrp";
		qcom,cpulist = <&CPU6 &CPU7>;

		cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,cpulist = <&CPU6 &CPU7>;
			qcom,target-dev = <&cpu6_cpu_l3_lat>;
			qcom,cachemiss-ev = <0x17>;
			qcom,stall-cycle-ev = <0x15E>;
			qcom,core-dev-table = <&cpu6_cpu_l3_tbl>;
		};

		cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,target-dev = <&cpu6_cpu_llcc_lat>;
			qcom,cachemiss-ev = <0x2A>;
			qcom,stall-cycle-ev = <0x15E>;
			qcom,core-dev-table =
				<  768000 MHZ_TO_MBPS(300, 16) >,
				< 1017600 MHZ_TO_MBPS(466, 16) >,
				< 1209600 MHZ_TO_MBPS(600, 16) >,
				< 1708800 MHZ_TO_MBPS(806, 16) >,
				< 2208000 MHZ_TO_MBPS(933, 16) >;
		};

		cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon {
			compatible = "qcom,arm-memlat-mon";
			qcom,cpulist = <&CPU6 &CPU7>;
			qcom,target-dev = <&cpu6_llcc_ddr_lat>;
			qcom,cachemiss-ev = <0x1000>;
			qcom,core-dev-table =
				<  768000 MHZ_TO_MBPS( 451, 4) >,
				< 1017600 MHZ_TO_MBPS( 547, 4) >,
				< 1209600 MHZ_TO_MBPS(1017, 4) >,
				< 1708800 MHZ_TO_MBPS(1555, 4) >,
				< 2208000 MHZ_TO_MBPS(1804, 4) >;
		};

		cpu6_computemon: qcom,cpu6-computemon {
			compatible = "qcom,arm-compute-mon";
			qcom,target-dev = <&cpu6_cpu_ddr_latfloor>;
			qcom,core-dev-table =
				< 1017600 MHZ_TO_MBPS( 300, 4) >,
				< 1209600 MHZ_TO_MBPS( 547, 4) >,
				< 1516800 MHZ_TO_MBPS( 768, 4) >,
				< 1708800 MHZ_TO_MBPS(1017, 4) >,
				< 2208000 MHZ_TO_MBPS(1804, 4) >;
		};
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,sm6150-pdc";
		reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			clock-frequency = <38400000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};

		scc_pll: scc_pll {
			compatible = "fixed-clock";
			clock-frequency = <600000000>;
			clock-output-names = "scc_pll";
			#clock-cells = <0>;
		};

		scc_pll_out_aux: scc_pll_out_aux {
			compatible = "fixed-factor-clock";
			clock-output-names = "scc_pll_out_aux";
			clocks = <&scc_pll>;
			clock-mult = <1>;
			clock-div = <2>;
			#clock-cells = <0>;
		};
	};

	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		qcom,irq-is-percpu;
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
	};

	dsu_pmu@0 {
		compatible = "arm,dsu-pmu";
		interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
		cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
		<&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
	};

	qcom,msm-imem@146aa000 {
		compatible = "qcom,msm-imem";
		reg = <0x146aa000 0x1000>;
		ranges = <0x0 0x146aa000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 0x8>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 0x4>;
		};

		dload_type@1c {
			compatible = "qcom,msm-imem-dload-type";
			reg = <0x1c 0x4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 0x20>;
		};

		kaslr_offset@6d0 {
			compatible = "qcom,msm-imem-kaslr_offset";
			reg = <0x6d0 0xc>;
		};

		pil@94c {
			compatible = "qcom,msm-imem-pil";
			reg = <0x94c 0xc8>;
		};

		diag_dload@c8 {
			compatible = "qcom,msm-imem-diag-dload";
			reg = <0xc8 0xc8>;
		};
	};

	restart@c264000 {
		compatible = "qcom,pshold";
		reg = <0xc264000 0x4>,
			<0x1fd3000 0x4>;
		reg-names = "pshold-base", "tcsr-boot-misc-detect";
	};

	qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>;
	};

	qcom,sps {
		compatible = "qcom,msm-sps-4k";
		qcom,pipe-attr-ee;
	};

	pil_scm_pas {
		compatible = "qcom,pil-tz-scm-pas";
		interconnects = <&aggre1_noc MASTER_CRYPTO
			&mc_virt SLAVE_EBI1>;
	};

	qcom,mpm2-sleep-counter@c221000 {
		compatible = "qcom,mpm2-sleep-counter";
		reg = <0xc221000 0x1000>;
		clock-frequency = <32768>;
	};

	cache-controller@9200000 {
		compatible = "qcom,sm6150-llcc";
		reg = <0x9200000 0x50000> , <0x9600000 0x50000>;
		reg-names = "llcc_base", "llcc_broadcast_base";
		cap-based-alloc-and-pwr-collapse;
	};

	mem_dump {
		compatible = "qcom,mem-dump";
		memory-region = <&dump_mem>;

		rpmh {
			qcom,dump-size = <0x2000000>;
			qcom,dump-id = <0xec>;
		};

		rpm_sw {
			qcom,dump-size = <0x28000>;
			qcom,dump-id = <0xea>;
		};

		pmic {
			qcom,dump-size = <0x10000>;
			qcom,dump-id = <0xe4>;
		};

		fcm {
			qcom,dump-size = <0x8400>;
			qcom,dump-id = <0xee>;
		};

		tmc_etf {
			qcom,dump-size = <0x8000>;
			qcom,dump-id = <0xf0>;
		};

		etf_swao {
			qcom,dump-size = <0x8000>;
			qcom,dump-id = <0xf1>;
		};

		etr_reg {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x100>;
		};

		etf_reg {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x101>;
		};

		etfswao_reg {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0x102>;
		};

		misc_data {
			qcom,dump-size = <0x1000>;
			qcom,dump-id = <0xe8>;
		};

		l1_icache0 {
			qcom,dump-size = <0x8800>;
			qcom,dump-id = <0x60>;
		};

		l1_icache100 {
			qcom,dump-size = <0x8800>;
			qcom,dump-id = <0x61>;
		};

		l1_icache200 {
			qcom,dump-size = <0x8800>;
			qcom,dump-id = <0x62>;
		};

		l1_icache300 {
			qcom,dump-size = <0x8800>;
			qcom,dump-id = <0x63>;
		};

		l1_icache400 {
			qcom,dump-size = <0x8800>;
			qcom,dump-id = <0x64>;
		};

		l1_icache500 {
			qcom,dump-size = <0x8800>;
			qcom,dump-id = <0x65>;
		};

		l1_icache600 {
			qcom,dump-size = <0x11000>;
			qcom,dump-id = <0x66>;
		};

		l1_icache700 {
			qcom,dump-size = <0x11000>;
			qcom,dump-id = <0x67>;
		};

		l1_dcache0 {
			qcom,dump-size = <0x9000>;
			qcom,dump-id = <0x80>;
		};

		l1_dcache100 {
			qcom,dump-size = <0x9000>;
			qcom,dump-id = <0x81>;
		};

		l1_dcache200 {
			qcom,dump-size = <0x9000>;
			qcom,dump-id = <0x82>;
		};

		l1_dcache300 {
			qcom,dump-size = <0x9000>;
			qcom,dump-id = <0x83>;
		};

		l1_dcache400 {
			qcom,dump-size = <0x9000>;
			qcom,dump-id = <0x84>;
		};

		l1_dcache500 {
			qcom,dump-size = <0x9000>;
			qcom,dump-id = <0x85>;
		};

		l1_dcache600 {
			qcom,dump-size = <0x12000>;
			qcom,dump-id = <0x86>;
		};

		l1_dcache700 {
			qcom,dump-size = <0x12000>;
			qcom,dump-id = <0x87>;
		};

		l1_itlb600 {
			qcom,dump-size = <0x300>;
			qcom,dump-id = <0x26>;
		};

		l1_itlb700 {
			qcom,dump-size = <0x300>;
			qcom,dump-id = <0x27>;
		};

		l1_dtlb600 {
			qcom,dump-size = <0x480>;
			qcom,dump-id = <0x46>;
		};

		l1_dtlb700 {
			qcom,dump-size = <0x480>;
			qcom,dump-id = <0x47>;
		};

		l2_cache600 {
			qcom,dump-size = <0x48000>;
			qcom,dump-id = <0xc6>;
		};

		l2_cache700 {
			qcom,dump-size = <0x48000>;
			qcom,dump-id = <0xc7>;
		};

		l2_tlb0 {
			qcom,dump-size = <0x5000>;
			qcom,dump-id = <0x120>;
		};

		l2_tlb100 {
			qcom,dump-size = <0x5000>;
			qcom,dump-id = <0x121>;
		};

		l2_tlb200 {
			qcom,dump-size = <0x5000>;
			qcom,dump-id = <0x122>;
		};

		l2_tlb300 {
			qcom,dump-size = <0x5000>;
			qcom,dump-id = <0x123>;
		};

		l2_tlb400 {
			qcom,dump-size = <0x5000>;
			qcom,dump-id = <0x124>;
		};

		l2_tlb500 {
			qcom,dump-size = <0x5000>;
			qcom,dump-id = <0x125>;
		};

		l2_tlb600 {
			qcom,dump-size = <0x7800>;
			qcom,dump-id = <0x126>;
		};

		l2_tlb700 {
			qcom,dump-size = <0x7800>;
			qcom,dump-id = <0x127>;
		};

		llcc1_d_cache {
			qcom,dump-size = <0x6c000>;
			qcom,dump-id = <0x140>;
		};
	};

	apps_rsc: rsc@18200000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x18200000 0x10000>,
		      <0x18210000 0x10000>,
		      <0x18220000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		qcom,tcs-offset = <0xd00>;
		qcom,drv-id = <2>;
		qcom,tcs-config = <ACTIVE_TCS  2>,
				  <SLEEP_TCS   3>,
				  <WAKE_TCS    3>,
				  <CONTROL_TCS 1>;

		apps_bcm_voter: bcm_voter {
			compatible = "qcom,bcm-voter";
		};

		rpmhcc: qcom,rpmhclk {
			compatible = "qcom,sm6150-rpmh-clk";
			#clock-cells = <1>;
			status = "okay";
		};

		system_pm {
			compatible = "qcom,system-pm";
		};
	};

	disp_rsc: rsc@af20000 {
		label = "disp_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0xaf20000 0x10000>;
		reg-names = "drv-0";
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
		qcom,tcs-offset = <0x1c00>;
		qcom,drv-id = <0>;
		qcom,tcs-config = <SLEEP_TCS   1>,
				  <WAKE_TCS    1>,
				  <ACTIVE_TCS  2>,
				  <CONTROL_TCS 0>;

		disp_bcm_voter: bcm_voter {
			compatible = "qcom,bcm-voter";
			qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
		};
	};

	camnoc_virt: interconnect@0 {
		compatible = "qcom,sm6150-camnoc_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	ipa_virt: interconnect@1 {
		compatible = "qcom,sm6150-ipa_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mc_virt: interconnect@2 {
		compatible = "qcom,sm6150-mc_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
	};

	dc_noc: interconnect@9160000 {
		reg = <0x9160000 0x3200>;
		compatible = "qcom,sm6150-dc_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	gem_noc: interconnect@9680000 {
		reg = <0x9680000 0x3E200>;
		compatible = "qcom,sm6150-gem_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
	};

	config_noc: interconnect@1500000 {
		reg = <0x1500000 0x5080>;
		compatible = "qcom,sm6150-config_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	system_noc: interconnect@1620000 {
		reg = <0x1620000 0x1F300>;
		compatible = "qcom,sm6150-system_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	aggre1_noc: interconnect@1700000 {
		reg = <0x1700000 0x3F200>;
		compatible = "qcom,sm6150-aggre1_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>,
			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
	};

	mmss_noc: interconnect@1740000 {
		reg = <0x1740000 0x1C100>;
		compatible = "qcom,sm6150-mmss_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
	};

	aopcc: qcom,aopcc@0 {
		compatible = "qcom,aop-qmp-clk";
		mboxes = <&qmp_aop 0>;
		mbox-names = "qdss_clk";
		#clock-cells = <1>;
	};

	gcc: clock-controller@100000 {
		compatible = "qcom,sm6150-gcc", "syscon";
		reg = <0x100000 0x1f0000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&rpmhcc RPMH_CXO_CLK_A>,
			<&sleep_clk>;
		clock-names = "bi_tcxo",
				"bi_tcxo_ao",
				"sleep_clk";
		protected-clocks = <GCC_SDR_CORE_CLK>,
				<GCC_SDR_WR0_MEM_CLK>,
				<GCC_SDR_WR1_MEM_CLK>,
				<GCC_SDR_WR2_MEM_CLK>,
				<GCC_SDR_CSR_HCLK>,
				<GCC_SDR_PRI_MI2S_CLK>,
				<GCC_SDR_SEC_MI2S_CLK>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	camcc: clock-controller@ad00000 {
		compatible = "qcom,sm6150-camcc", "syscon";
		reg = <0xad00000 0x10000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "bi_tcxo";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc: clock-controller@af00000 {
		compatible = "qcom,sm6150-dispcc", "syscon";
		reg = <0xaf00000 0x20000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
		clock-names = "bi_tcxo", "gpll0";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpucc: clock-controller@5090000 {
		compatible = "qcom,sm6150-gpucc", "syscon";
		reg = <0x5090000 0x9000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mx-supply = <&VDD_MX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
		clock-names = "bi_tcxo", "gpll0";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	scc: clock-controller@62b10000 {
		compatible = "qcom,sa6155-scc", "syscon";
		reg = <0x62b10000 0x30000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&sleep_clk>, <&scc_pll>,
			<&scc_pll_out_aux>;
		clock-names = "bi_tcxo", "sleep_clk",
			"scc_pll", "scc_pll_out_aux";
		#clock-cells = <1>;
		#reset-cells = <1>;
		status = "disabled";
	};

	videocc: clock-controller@ab00000 {
		compatible = "qcom,sm6150-videocc", "syscon";
		reg = <0xab00000 0x10000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
		clock-names = "bi_tcxo", "sleep_clk";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	apsscc: syscon@182a0000 {
		compatible = "syscon";
		reg = <0x182a0000 0x1c>;
	};

	mccc: syscon@90b0000 {
		compatible = "syscon";
		reg = <0x90b0000 0x54>;
	};

	debugcc: debug-clock-controller@0 {
		compatible = "qcom,sm6150-debugcc";
		qcom,apsscc = <&apsscc>;
		qcom,camcc = <&camcc>;
		qcom,dispcc = <&dispcc>;
		qcom,gcc = <&gcc>;
		qcom,gpucc = <&gpucc>;
		qcom,mccc = <&mccc>;
		qcom,videocc = <&videocc>;
		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo_clk_src";
		#clock-cells = <1>;
	};

	cpufreq_hw: cpufreq@18323000 {
		compatible = "qcom,cpufreq-hw";
		reg = <0x18323000 0x1400>, <0x18325800 0x1400>;
		reg-names = "freq-domain0", "freq-domain1";
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
		clock-names = "xo", "alternate";
		qcom,no-accumulative-counter;
		#freq-domain-cells = <2>;
	};

	camnoc_virt: interconnect@0 {
		compatible = "qcom,sm6150-camnoc_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	ipa_virt: interconnect@1 {
		compatible = "qcom,sm6150-ipa_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mc_virt: interconnect@2 {
		compatible = "qcom,sm6150-mc_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
	};

	dc_noc: interconnect@9160000 {
		reg = <0x9160000 0x3200>;
		compatible = "qcom,sm6150-dc_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	gem_noc: interconnect@9680000 {
		reg = <0x9680000 0x3E200>;
		compatible = "qcom,sm6150-gem_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
	};

	config_noc: interconnect@1500000 {
		reg = <0x1500000 0x5080>;
		compatible = "qcom,sm6150-config_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	system_noc: interconnect@1620000 {
		reg = <0x1620000 0x1F300>;
		compatible = "qcom,sm6150-system_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	aggre1_noc: interconnect@1700000 {
		reg = <0x1700000 0x3F200>;
		compatible = "qcom,sm6150-aggre1_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mmss_noc: interconnect@1740000 {
		reg = <0x1740000 0x1C100>;
		compatible = "qcom,sm6150-mmss_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
	};

	osm_l3: interconnect@18321000 {
		reg = <0x18321000 0x1400>;
		compatible = "qcom,sm6150-osm-l3";
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
		clock-names = "xo", "alternate";
		#interconnect-cells = <1>;
	};

	spmi_bus: qcom,spmi@c440000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc440000 0x1100>,
		      <0xc600000 0x2000000>,
		      <0xe600000 0x100000>,
		      <0xe700000 0xa0000>,
		      <0xc40a000 0x26000>;
		reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "periph_irq";
		interrupt-controller;
		#interrupt-cells = <4>;
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,channel = <0>;
		qcom,ee = <0>;
	};

	thermal_zones: thermal-zones {
	};

	ufsphy_mem: ufsphy_mem@1d87000 {
		reg = <0x1d87000 0xe00>; /* PHY regs */
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <1>;

		clock-names = "ref_clk_src",
			"ref_clk",
			"ref_aux_clk";
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_UFS_MEM_CLKREF_CLK>,
			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

		resets = <&ufshc_mem 0>;
		status = "disabled";
	};

	thermal_zones: thermal-zones {
	};

	ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x3000>,
			  <0x1d90000 0x8000>;
		reg-names = "ufs_mem", "ufs_ice";
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";
		#reset-cells = <1>;

		lanes-per-direction = <1>;
		limit-phy-submode = <0>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */
		spm-level = <5>;

		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk";
		clocks =
			<&gcc GCC_UFS_PHY_AXI_CLK>,
			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&gcc GCC_UFS_PHY_AHB_CLK>,
			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
		freq-table-hz =
			<50000000 200000000>,
			<0 0>,
			<0 0>,
			<37500000 150000000>,
			<75000000 300000000>,
			<0 0>,
			<0 0>,
			<0 0>;

		interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
		interconnect-names = "ufs-ddr", "cpu-ufs";

		qcom,ufs-bus-bw,name = "ufshc_mem";
		qcom,ufs-bus-bw,num-cases = <12>;
		qcom,ufs-bus-bw,num-paths = <2>;
		qcom,ufs-bus-bw,vectors-KBps =
		/*
		 * During HS G3 UFS runs at nominal voltage corner, vote
		 * higher bandwidth to push other buses in the data path
		 * to run at nominal to achieve max throughput.
		 * 4GBps pushes BIMC to run at nominal.
		 * 200MBps pushes CNOC to run at nominal.
		 * Vote for half of this bandwidth for HS G3 1-lane.
		 * For max bandwidth, vote high enough to push the buses
		 * to run in turbo voltage corner.
		 */
		<0 0>, <0 0>,          /* No vote */
		<922 0>, <1000 0>,     /* PWM G1 */
		<1844 0>, <1000 0>,    /* PWM G2 */
		<3688 0>, <1000 0>,    /* PWM G3 */
		<7376 0>, <1000 0>,    /* PWM G4 */
		<127796 0>, <1000 0>,  /* HS G1 RA */
		<255591 0>, <1000 0>,  /* HS G2 RA */
		<2097152 0>, <102400 0>,  /* HS G3 RA */
		<149422 0>, <1000 0>,  /* HS G1 RB */
		<298189 0>, <1000 0>,  /* HS G2 RB */
		<2097152 0>, <102400 0>,  /* HS G3 RB */
		<7643136 0>, <307200 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",
		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
		"MAX";

		reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>;

		resets = <&gcc GCC_UFS_PHY_BCR>;
		reset-names = "rst";
		non-removable;

		status = "disabled";
		qos0 {
			mask = <0xc0>;
			vote = <67>;
		};

		qos1 {
			mask = <0x3f>;
			vote = <67>;
		};
	};

	qmp_aop: qcom,qmp-aop@c300000 {
		compatible = "qcom,qmp-mbox";
		reg = <0xc300000 0x1000>, <0x17c0000C 0x4>;
		reg-names = "msgram", "irq-reg-base";
		qcom,irq-mask = <0x1>;
		interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;

		label = "aop";
		qcom,early-boot;
		priority = <0>;
		mbox-desc-offset = <0x0>;
		#mbox-cells = <1>;
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr_mutex: hwlock@1f40000 {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem: qcom,smem@8600000 {
		compatible = "qcom,smem";
		memory-region = <&smem_region>;
		hwlocks = <&tcsr_mutex 3>;
	};

	apcs: syscon@17c0000c {
		compatible = "syscon";
		reg = <0x17c0000c 0x4>;
	};

	apss_shared: mailbox@17c00000 {
		compatible = "qcom,sm8150-apss-shared";
		reg = <0x17c00000 0x1000>;

		#mbox-cells = <1>;
	};

	qcom,msm-cdsp-loader {
		compatible = "qcom,cdsp-loader";
		qcom,proc-img-to-load = "cdsp";
	};

	qcom,msm-adsprpc-mem {
		compatible = "qcom,msm-adsprpc-mem-region";
		memory-region = <&adsp_mem>;
		restrict-access;
	};

	qcom,msm_fastrpc {
		compatible = "qcom,msm-fastrpc-compute";
		qcom,rpc-latency-us = <611>;
		qcom,adsp-remoteheap-vmid = <22 37>;
		qcom,fastrpc-adsp-audio-pdr;
		qcom,fastrpc-adsp-sensors-pdr;

		qcom,msm_fastrpc_compute_cb1 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1081 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb2 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1082 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb3 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1083 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb4 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1084 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb5 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1085 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb6 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1086 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb9 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			qcom,secure-context-bank;
			iommus = <&apps_smmu 0x1089 0x0>;
			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb10 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1723 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb11 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1724 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb12 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1725 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};

		qcom,msm_fastrpc_compute_cb13 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1726 0x0>;
			shared-cb = <5>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable";
			dma-coherent-hint-cached;
		};
	};

	qcom,glink {
		compatible = "qcom,glink";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		glink_modem: modem {
			qcom,remote-pid = <1>;
			transport = "smem";
			mboxes = <&apss_shared 12>;
			mbox-names = "mpss_smem";
			interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;

			label = "modem";
			qcom,glink-label = "mpss";

			qcom,modem_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,low-latency;
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,modem_ds {
				qcom,glink-channels = "DS";
				qcom,intents = <0x4000 0x2>;
			};

			qcom,modem_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_adsp>,
						    <&glink_cdsp>;
			};
		};

		glink_adsp: adsp {
			qcom,remote-pid = <2>;
			transport = "smem";
			mboxes = <&apss_shared 24>;
			mbox-names = "adsp_smem";
			interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;

			label = "adsp";
			qcom,glink-label = "lpass";

			qcom,adsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,apr_tal_rpmsg {
				qcom,glink-channels = "apr_audio_svc";
				qcom,intents = <0x200 20>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,adsp_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_modem>,
						    <&glink_cdsp>;
			};
		};

		glink_cdsp: cdsp {
			qcom,remote-pid = <5>;
			transport = "smem";
			mboxes = <&apss_shared 4>;
			mbox-names = "cdsp_smem";
			interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;

			label = "cdsp";
			qcom,glink-label = "cdsp";

			qcom,cdsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,msm_cdsprm_rpmsg {
				compatible = "qcom,msm-cdsprm-rpmsg";
				qcom,glink-channels = "cdsprmglink-apps-dsp";
				qcom,intents = <0x20 12>;

				qcom,cdsp-cdsp-l3-gov {
					compatible = "qcom,cdsp-l3";
				/*	qcom,target-dev = <&cdsp_cdsp_l3_lat>;*/
				};

				msm_cdsp_rm: qcom,msm_cdsp_rm {
					compatible = "qcom,msm-cdsp-rm";
					qcom,qos-latency-us = <44>;
					qcom,qos-maxhold-ms = <20>;
					#cooling-cells = <2>;
				};

				msm_hvx_rm: qcom,msm_hvx_rm {
					compatible = "qcom,msm-hvx-rm";
					#cooling-cells = <2>;
				};
			};

			qcom,cdsp_glink_ssr {
				qcom,glink-channels = "glink_ssr";
				qcom,notify-edges = <&glink_modem>,
						    <&glink_adsp>;
			};
		};

		glink_spi_xprt_wdsp: wdsp {
			transport = "spi";
			tx-descriptors = <0x12000 0x12004>;
			rx-descriptors = <0x1200c 0x12010>;

			label = "wdsp";
			qcom,glink-label = "wdsp";

			qcom,wdsp_ctrl {
				qcom,glink-channels = "g_glink_ctrl";
				qcom,intents = <0x400 1>;
			};

			qcom,wdsp_ild {
				qcom,glink-channels =
					"g_glink_persistent_data_ild";
			};

			qcom,wdsp_nild {
				qcom,glink-channels =
					"g_glink_persistent_data_nild";
			};

			qcom,wdsp_data {
				qcom,glink-channels = "g_glink_audio_data";
				qcom,intents = <0x1000 2>;
			};

			qcom,diag_data {
				qcom,glink-channels = "DIAG_DATA";
				qcom,intents = <0x4000 2>;
			};

			qcom,diag_ctrl {
				qcom,glink-channels = "DIAG_CTRL";
				qcom,intents = <0x4000 1>;
			};

			qcom,diag_cmd {
				qcom,glink-channels = "DIAG_CMD";
				qcom,intents = <0x4000 1>;
			};
		};
	};

	qcom,glinkpkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-at-mdm0 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DS";
			qcom,glinkpkt-dev-name = "at_mdm0";
		};

		qcom,glinkpkt-apr-apps2 {
			qcom,glinkpkt-edge = "adsp";
			qcom,glinkpkt-ch-name = "apr_apps2";
			qcom,glinkpkt-dev-name = "apr_apps2";
		};

		qcom,glinkpkt-data40-cntl {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA40_CNTL";
			qcom,glinkpkt-dev-name = "smdcntl8";
		};

		qcom,glinkpkt-data1 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA1";
			qcom,glinkpkt-dev-name = "smd7";
		};

		qcom,glinkpkt-data4 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA4";
			qcom,glinkpkt-dev-name = "smd8";
		};

		qcom,glinkpkt-data11 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA11";
			qcom,glinkpkt-dev-name = "smd11";
		};
	};

	qcom,smp2p_sleepstate {
		compatible = "qcom,smp2p-sleepstate";
		qcom,smem-states = <&sleepstate_smp2p_out 0>;
		interrupt-parent = <&sleepstate_smp2p_in>;
		interrupts = <0 0>;
		interrupt-names = "smp2p-sleepstate-in";
	};

	qcom,smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
		qcom,ipc = <&apcs 0 14>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		/* ipa - inbound entry from mss */
		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
			qcom,entry-name = "wlan";
			interrupt-controller;
			#interrupt-cells = <2>;
		 };
	};

	qcom,smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
		qcom,ipc = <&apcs 0 26>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sleepstate_smp2p_out: sleepstate-out {
			qcom,entry-name = "sleepstate";
			#qcom,smem-state-cells = <1>;
		};

		sleepstate_smp2p_in: qcom,sleepstate-in {
			qcom,entry-name = "sleepstate_see";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
		qcom,ipc = <&apcs 0 6>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,lpass@62400000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x62400000 0x00100>;

		vdd_cx-supply = <&L8A_LEVEL>;
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		qcom,proxy-reg-names = "vdd_cx";

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";

		qcom,pas-id = <1>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <423>;
		qcom,sysmon-id = <1>;
		qcom,ssctl-instance-id = <0x14>;
		qcom,firmware-name = "adsp";
		memory-region = <&pil_adsp_mem>;
		qcom,signal-aop;
		qcom,complete-ramdump;

		/* Inputs from lpass */
		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
						<&adsp_smp2p_in 0 0>,
						<&adsp_smp2p_in 2 0>,
						<&adsp_smp2p_in 1 0>,
						<&adsp_smp2p_in 3 0>,
						<&adsp_smp2p_in 7 0>;
		interrupt-names = "qcom,wdog",
						"qcom,err-fatal",
						"qcom,proxy-unvote",
						"qcom,err-ready",
						"qcom,stop-ack",
						"qcom,shutdown-ack";

		/* Outputs to lpass */
		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";

		mboxes = <&qmp_aop 0>;
		mbox-names = "adsp-pil";
	};
	qcom,turing@8300000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0x8300000 0x100000>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,proxy-reg-names = "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";

		qcom,pas-id = <18>;
		qcom,proxy-timeout-ms = <10000>;
		qcom,smem-id = <601>;
		qcom,sysmon-id = <7>;
		qcom,ssctl-instance-id = <0x17>;
		qcom,firmware-name = "cdsp";
		memory-region = <&pil_cdsp_mem>;
		qcom,signal-aop;
		qcom,complete-ramdump;

		/* Inputs from turing */
		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
						<&cdsp_smp2p_in 0 0>,
						<&cdsp_smp2p_in 2 0>,
						<&cdsp_smp2p_in 1 0>,
						<&cdsp_smp2p_in 3 0>,
						<&cdsp_smp2p_in 7 0>;

		interrupt-names = "qcom,wdog",
						"qcom,err-fatal",
						"qcom,proxy-unvote",
						"qcom,err-ready",
						"qcom,stop-ack",
						"qcom,shutdown-ack";

		/* Outputs to turing */
		qcom,smem-states = <&cdsp_smp2p_out 0>;
		qcom,smem-state-names = "qcom,force-stop";

		mboxes = <&qmp_aop 0>;
		mbox-names = "cdsp-pil";
	};

	qcom,venus@aae0000 {
		compatible = "qcom,pil-tz-generic";
		reg = <0xaae0000 0x4000>;

		vdd-supply = <&venus_gdsc>;
		qcom,proxy-reg-names = "vdd";

		clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
				<&videocc VIDEO_CC_VENUS_AHB_CLK>,
				<&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
		clock-names = "core_clk", "iface_clk", "bus_clk";
		qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk";

		qcom,pas-id = <9>;
		interconnect-names  = "pil-venus";
		interconnects = <&mmss_noc MASTER_VIDEO_P0
				&mc_virt SLAVE_EBI1>;
		qcom,proxy-timeout-ms = <100>;
		qcom,firmware-name = "venus";
		memory-region = <&pil_video_mem>;
	};

	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
	};

	qcom_qseecom: qseecom@86d00000 {
		compatible = "qcom,qseecom";
		reg = <0x86d00000 0xe00000>;
		reg-names = "secapp-region";
		memory-region = <&qseecom_mem>;
		qcom,hlos-num-ce-hw-instances = <1>;
		qcom,hlos-ce-hw-instance = <0>;
		qcom,qsee-ce-hw-instance = <0>;
		qcom,disk-encrypt-pipe-pair = <2>;
		qcom,support-fde;
		qcom,no-clock-support;
		qcom,fde-key-size;
		qcom,appsbl-qseecom-support;
		qcom,commonlib64-loaded-by-uefi;
		qcom,qsee-reentrancy-support = <2>;
	};

	qcom_smcinvoke: smcinvoke@86d00000 {
		compatible = "qcom,smcinvoke";
		reg = <0x86d00000 0xe00000>;
		reg-names = "secapp-region";
	};

	qcom_rng: qrng@793000 {
		compatible = "qcom,msm-rng";
		reg = <0x793000 0x1000>;
		qcom,msm-rng-iface-clk;
		qcom,no-qrng-config;
		interconnect-names = "data_path";
		interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_PRNG>;
		clock-names = "km_clk_src";
		clocks = <&gcc GCC_PRNG_AHB_CLK>;
	};

	qcom_tzlog: tz-log@146aa720 {
		compatible = "qcom,tz-log";
		reg = <0x146aa720 0x3000>;
		qcom,hyplog-enabled;
		hyplog-address-offset = <0x410>;
		hyplog-size-offset = <0x414>;
	};

	sdhc_1: sdhci@7c4000 {
		compatible = "qcom,sdhci-msm-v5";
		reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7C8000 0x8000>;
		reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";

		interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		clocks = <&gcc GCC_SDCC1_AHB_CLK>,
			<&gcc GCC_SDCC1_APPS_CLK>,
			<&gcc GCC_SDCC1_ICE_CORE_CLK>;
		clock-names = "iface", "core", "ice_core";

		qcom,ice-clk-rates = <300000000 75000000>;

		qcom,devfreq,freq-table = <50000000 200000000>;

		bus-width = <8>;
		qcom,restore-after-cx-collapse;
		supports-cqe;

		mmc-ddr-1_8v;
		mmc-hs200-1_8v;
		mmc-hs400-1_8v;
		mmc-hs400-enhanced-strobe;
		non-removable;

		interconnects = <&aggre1_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_1>;
		interconnect-names = "sdhc-ddr","cpu-sdhc";

		qcom,msm-bus,name = "sdhc1";
		qcom,msm-bus,num-cases = <6>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-KBps =
			/* No vote */
			<0 0>, <0 0>,
			/* 50 MB/s */
			<130718 200000>,<133320 133320>,
			/* 100 MB/s */
			<130718 200000>,<150000 150000>,
			/* 200 MB/s */
			<261438 400000>,<300000 300000>,
			/* 400 MB/s */
			<261438 2718822>,<300000 1359411>,
			/* Max. bandwidth */
			<1338562 4096000>,<1338562 4096000>;
		qcom,bus-bw-vectors-bps = <0 50000000 100750000
				200000000 400000000 4294967295>;

		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x000F642C 0x0 0x0 0x00010800 0x80040868>;

		status = "disabled";

		qos0 {
			mask = <0x3f>;
			vote = <67>;
		};

		qos1 {
			mask = <0xc0>;
			vote = <67>;
		};
	};

	sdhc_2: sdhci@8804000 {
		compatible = "qcom,sdhci-msm-v5";
		reg = <0x8804000 0x1000>;
		reg-names = "hc_mem";

		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
			<&gcc GCC_SDCC2_APPS_CLK>;
		clock-names = "iface", "core";

		bus-width = <4>;
		qcom,restore-after-cx-collapse;

		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x0007642C 0x0 0x0 0x00010800 0x80040868>;

		qcom,devfreq,freq-table = <50000000 202000000>;

		interconnects = <&aggre1_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
		interconnect-names = "sdhc-ddr","cpu-sdhc";

		qcom,msm-bus,name = "sdhc2";
		qcom,msm-bus,num-cases = <6>;
		qcom,msm-bus,num-paths = <2>;
		qcom,msm-bus,vectors-KBps =
			/* No vote */
			<0 0>, <0 0>,
			/* 25 MB/s */
			<65360 100000>,<100000 100000>,
			/* 50 MB/s */
			<130718 200000>,<133320 133320>,
			/* 100 MB/s */
			<261438 200000>,<150000 150000>,
			/* 200 MB/s */
			<261438 400000>,<300000 300000>,
			/* Max. bandwidth */
			<1338562 4096000>,<1338562 4096000>;
		qcom,bus-bw-vectors-bps = <0 25000000 50000000
			100750000 200000000 4294967295>;

		status = "disabled";

		qos0 {
			mask = <0x3f>;
			vote = <67>;
		};

		qos1 {
			mask = <0xc0>;
			vote = <67>;
		};
	};

	qcom,rmtfs_sharedmem@0 {
		compatible = "qcom,sharedmem-uio";
		reg = <0x0 0x200000>;
		reg-names = "rmtfs";
		qcom,client-id = <0x00000001>;
		qcom,guard-memory;
	};

	wdog: qcom,wdt@17c10000 {
		compatible = "qcom,msm-watchdog";
		reg = <0x17c10000 0x1000>;
		reg-names = "wdt-base";
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bark-time = <11000>;
		qcom,pet-time = <9360>;
		qcom,ipi-ping;
		qcom,wakeup-enable;
	};

	qcom,chd_sliver {
		compatible = "qcom,core-hang-detect";
		label = "silver";
		qcom,threshold-arr = <0x18000058 0x18010058 0x18020058
					0x18030058 0x18040058 0x18050058>;
		qcom,config-arr = <0x18000060 0x18010060 0x18020060
					0x18030060 0x18040060 0x18050060>;
	};

	qcom,chd_gold {
		compatible = "qcom,core-hang-detect";
		label = "gold";
		qcom,threshold-arr = <0x18060058 0x18070058>;
		qcom,config-arr = <0x18060060 0x18070060>;
	};

	aop-set-ddr-freq {
		compatible = "qcom,aop-set-ddr-freq";
		mboxes = <&qmp_aop 0>;
		mbox-names = "aop";
	};

	cx_ipeak_lm: cx_ipeak@01fed000 {
		compatible = "qcom,cx-ipeak-v1";
		reg = <0x1fed000 0x28>;
	};
};

&firmware {
	scm {
		compatible = "qcom,scm";
	};
};

#include "sm6150-qupv3.dtsi"
#include "sm6150-ssc-qupv3.dtsi"
#include "sm6150-pinctrl.dtsi"
#include "sm6150-pm.dtsi"
#include "sm6150-regulator.dtsi"
#include "sm6150-gdsc.dtsi"

&firmware {
	scm {
		compatible = "qcom,scm";
	};
};

&emac_gdsc {
	status = "ok";
};

&pcie_0_gdsc {
	status = "ok";
};

&ufs_phy_gdsc {
	status = "ok";
};

&usb30_prim_gdsc {
	status = "ok";
};

&usb20_sec_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
	status = "ok";
};

&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
	status = "ok";
};

&bps_gdsc {
	qcom,support-hw-trigger;
	status = "ok";
};

&ife_0_gdsc {
	status = "ok";
};

&ife_1_gdsc {
	status = "ok";
};

&ipe_0_gdsc {
	qcom,support-hw-trigger;
	status = "ok";
};

&titan_top_gdsc {
	status = "ok";
};

&mdss_core_gdsc {
	status = "ok";
};

&gpu_cx_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gpu_gx_gdsc {
	clock-names = "core_root_clk";
	clocks = <&gpucc GPU_CC_GX_GFX3D_CLK_SRC>;
	qcom,force-enable-root-clk;
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&vcodec0_gdsc {
	qcom,support-hw-trigger;
	status = "ok";
};

&venus_gdsc {
	status = "ok";
};

#include "msm-arm-smmu-sm6150.dtsi"
#include "sm6150-slpi-pinctrl.dtsi"
#include "sm6150-gpu.dtsi"
#include "sm6150-usb.dtsi"
#include "sm6150-vidc.dtsi"
#include "sm6150-ion.dtsi"
#include "sm6150-thermal.dtsi"
#include "camera/sm6150-camera.dtsi"