mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-12 10:01:54 -05:00
685 lines
14 KiB
Devicetree
685 lines
14 KiB
Devicetree
#include <dt-bindings/clock/qcom,aop-qmp.h>
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#include <dt-bindings/clock/qcom,camcc-yupik.h>
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#include <dt-bindings/clock/qcom,dispcc-yupik.h>
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#include <dt-bindings/clock/qcom,gcc-yupik.h>
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#include <dt-bindings/clock/qcom,gpucc-yupik.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,videocc-yupik.h>
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#include <dt-bindings/interconnect/qcom,epss-l3.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,yupik.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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/ {
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model = "Qualcomm Technologies, Inc. Yupik";
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compatible = "qcom,yupik";
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qcom,msm-id = <475 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases { };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: hyp@80000000 {
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no-map;
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reg = <0x0 0x80000000 0x0 0x600000>;
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};
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xbl_aop_mem: xbl_aop_mem@80700000 {
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no-map;
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reg = <0x0 0x80700000 0x0 0x160000>;
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};
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cmd_db: cmd_db@80860000 {
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compatible = "qcom,cmd-db";
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no-map;
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reg = <0x0 0x80860000 0x0 0x20000>;
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};
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reserved_xbl_uefi: reserved_xbl_uefi@80880000 {
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no-map;
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reg = <0x0 0x80880000 0x0 0x14000>;
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};
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secdata_apss_mem: secdata_apss@808ff000 {
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no-map;
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reg = <0x0 0x808ff000 0x0 0x1000>;
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};
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smem_mem: smem@80900000 {
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no-map;
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reg = <0x0 0x80900000 0x0 0x200000>;
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};
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fw_mem: fw@80b00000 {
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no-map;
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reg = <0x0 0x80b00000 0x0 0x100000>;
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};
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wlan_fw_mem: wlan_fw@80c00000 {
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no-map;
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reg = <0x0 0x80c00000 0x0 0xc00000>;
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};
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cdsp_secure_heap_mem: cdsp_secure_heap@81800000 {
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no-map;
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reg = <0x0 0x81800000 0x0 0x1e00000>;
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};
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pil_cvp_mem: camera@86200000 {
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no-map;
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reg = <0x0 0x86200000 0x0 0x500000>;
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};
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pil_adsp_mem: adsp@86700000 {
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no-map;
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reg = <0x0 0x86700000 0x0 0x2800000>;
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};
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pil_cdsp_mem: cdsp@88f00000 {
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no-map;
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reg = <0x0 0x88f00000 0x0 0x1e00000>;
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};
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pil_camera_mem: video@8ad00000 {
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no-map;
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reg = <0x0 0x8ad00000 0x0 0x500000>;
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};
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pil_video_mem: cvp@8b200000 {
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no-map;
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reg = <0x0 0x8b200000 0x0 0x500000>;
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};
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pil_ipa_fw_mem: ipa_fw@8b700000 {
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no-map;
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reg = <0x0 0x8b700000 0x0 0x10000>;
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};
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pil_ipa_gsi_mem: ipa_gsi@8b710000 {
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no-map;
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reg = <0x0 0x8b710000 0x0 0xa000>;
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};
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pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 {
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no-map;
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reg = <0x0 0x8b71a000 0x0 0x2000>;
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};
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pil_mpss_mem: mpss@8b800000 {
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no-map;
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reg = <0x0 0x8b800000 0x0 0xf600000>;
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};
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pil_wpss_mem: wlan@9ae00000 {
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no-map;
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reg = <0x0 0x9ae00000 0x0 0x1900000>;
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};
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removed_mem: removed_region@c0000000 {
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no-map;
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reg = <0x0 0xc0000000 0x0 0x5100000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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soc: soc { };
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chosen { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17a00000 0x10000>, /* GICD */
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<0x17a60000 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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wdog: qcom,wdt@17c10000 {
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compatible = "qcom,msm-watchdog";
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reg = <0x17c10000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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ipcc_mproc: qcom,ipcc@408000 {
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compatible = "qcom,ipcc";
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reg = <0x408000 0x1000>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@17c20000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17c20000 0x1000>;
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clock-frequency = <19200000>;
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frame@17c21000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c21000 0x1000>,
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<0x17c22000 0x1000>;
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};
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frame@17c23000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c23000 0x1000>;
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status = "disabled";
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};
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frame@17c25000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c25000 0x1000>;
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status = "disabled";
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};
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frame@17c27000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c27000 0x1000>;
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status = "disabled";
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};
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frame@17c29000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c29000 0x1000>;
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status = "disabled";
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};
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frame@17c2b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c2b000 0x1000>;
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status = "disabled";
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};
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frame@17c2d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c2d000 0x1000>;
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status = "disabled";
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};
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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clock-frequency = <76800000>;
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clock-output-names = "xo_board";
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#clock-cells = <0>;
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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clock-output-names = "sleep_clk";
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#clock-cells = <0>;
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};
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pcie_0_pipe_clk: pcie-0-pipe-clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_0_pipe_clk";
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#clock-cells = <0>;
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};
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pcie_1_pipe_clk: pcie-1-pipe-clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "pcie_1_pipe_clk";
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#clock-cells = <0>;
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};
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usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
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compatible = "fixed-clock";
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clock-frequency = <1000>;
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clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
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#clock-cells = <0>;
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};
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};
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bi_tcxo: bi_tcxo {
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compatible = "fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <4>;
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clocks = <&xo_board>;
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#clock-cells = <0>;
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};
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bi_tcxo_ao: bi_tcxo_ao {
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compatible = "fixed-factor-clock";
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clock-mult = <1>;
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clock-div = <4>;
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clocks = <&xo_board>;
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#clock-cells = <0>;
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};
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aopcc: qcom,aopcc {
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compatible = "qcom,dummycc";
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clock-output-names = "aopcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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rpmhcc: qcom,rpmhcc {
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compatible = "qcom,dummycc";
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clock-output-names = "rpmhcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gcc: clock-controller@100000 {
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compatible = "qcom,dummycc";
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clock-output-names = "gcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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camcc: clock-controller@ad00000 {
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compatible = "qcom,dummycc";
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clock-output-names = "camcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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dispcc: clock-controller@af00000 {
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compatible = "qcom,dummycc";
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clock-output-names = "dispcc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gpucc: clock-controller@3d90000 {
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compatible = "qcom,dummycc";
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clock-output-names = "gpucc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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videocc: clock-controller@aaf0000 {
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compatible = "qcom,dummycc";
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clock-output-names = "videocc_clocks";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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clk_virt: interconnect {
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compatible = "qcom,yupik-clk_virt";
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#interconnect-cells = <1>;
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};
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config_noc: interconnect@1500000 {
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compatible = "qcom,yupik-config_noc";
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#interconnect-cells = <1>;
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};
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mc_virt: interconnect@1580000 {
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compatible = "qcom,yupik-mc_virt";
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#interconnect-cells = <1>;
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};
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system_noc: interconnect@1680000 {
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compatible = "qcom,yupik-system_noc";
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#interconnect-cells = <1>;
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};
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aggre1_noc: interconnect@16e0000 {
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compatible = "qcom,yupik-aggre1_noc";
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#interconnect-cells = <1>;
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};
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aggre2_noc: interconnect@1700000 {
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compatible = "qcom,yupik-aggre2_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
mmss_noc: interconnect@1740000 {
|
|
compatible = "qcom,yupik-mmss_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
lpass_ag_noc: interconnect@3c40000 {
|
|
compatible = "qcom,yupik-lpass_ag_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
dc_noc: interconnect@90e0000 {
|
|
compatible = "qcom,yupik-dc_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
gem_noc: interconnect@9100000 {
|
|
compatible = "qcom,yupik-gem_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
nsp_noc: interconnect@a0c0000 {
|
|
compatible = "qcom,yupik-nsp_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
epss_l3_cpu: l3_cpu@18590000 {
|
|
compatible = "qcom,yupik-epss-l3-cpu";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
};
|
|
|
|
#include "shima-gdsc.dtsi"
|
|
#include "yupik-pinctrl.dtsi"
|
|
#include "yupik-stub-regulator.dtsi"
|
|
|
|
&gcc_pcie_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&gcc_pcie_1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&gcc_ufs_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&gcc_usb30_prim_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&gcc_usb30_sec_gdsc {
|
|
compatible = "regulator-fixed";
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&cam_cc_titan_top_gdsc {
|
|
compatible = "regulator-fixed";
|
|
reg = <0xad0c194 0x4>;
|
|
status = "ok"
|
|
};
|
|
|
|
&cam_cc_bps_gdsc {
|
|
compatible = "regulator-fixed";
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&cam_cc_ife_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&cam_cc_ife_1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&cam_cc_ife_2_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&cam_cc_ipe_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&disp_cc_mdss_core_gdsc {
|
|
compatible = "regulator-fixed";
|
|
reg = <0xaf01004 0x4>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&gpu_cx_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&gpu_gx_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&video_cc_mvs0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
reg = <0xaaf3004 0x4>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&video_cc_mvsc_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|