mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-24 21:54:34 -04:00
501 lines
14 KiB
Devicetree
501 lines
14 KiB
Devicetree
#include <dt-bindings/clock/qcom,gcc-lahaina.h>
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&soc {
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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reg = <0x01c00000 0x3000>,
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<0x01c06000 0x2000>,
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<0x60000000 0xf1d>,
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<0x60000f20 0xa8>,
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<0x60001000 0x1000>,
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<0x60100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0_msi>;
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perst-gpio = <&tlmm 94 0>;
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wake-gpio = <&tlmm 96 0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_perst_default
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&pcie0_clkreq_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_perst_default
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&pcie0_clkreq_sleep
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&pcie0_wake_default>;
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gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;
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vreg-1p8-supply = <&pm8350_l6>;
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vreg-0p9-supply = <&pm8350_l5>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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qcom,vreg-1p8-voltage-level = <1200000 1200000 15000>;
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qcom,vreg-0p9-voltage-level = <880000 880000 47900>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_NOM
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000>;
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interconnect-names = "icc_path";
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interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
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clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_PCIE_0_AUX_CLK>,
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<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&clock_gcc GCC_PCIE_0_CLKREF_EN>,
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<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
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<&clock_gcc GCC_PCIE0_PHY_RCHNG_CLK>,
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<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
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<&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
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<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
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<&clock_gcc GCC_PCIE_0_PIPE_CLK_SRC>,
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<&clock_gcc PCIE_0_PIPE_CLK>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_tbu_clk", "pcie_phy_refgen_clk",
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"pcie_ddrss_sf_tbu_clk",
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"pcie_aggre_noc_0_axi_clk",
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"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
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"pcie_pipe_clk_ext_src";
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max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>, <0>,
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<0>, <0>, <0>, <0>;
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resets = <&clock_gcc GCC_PCIE_0_BCR>,
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<&clock_gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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dma-coherent;
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qcom,smmu-sid-base = <0x1c00>;
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iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
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<0x100 &apps_smmu 0x1c01 0x1>;
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qcom,boot-option = <0x1>;
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qcom,aux-clk-freq = <20>; /* 19.2 MHz */
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qcom,drv-supported;
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qcom,l1ss-sleep-disable = <0x1>;
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qcom,drv-l1ss-timeout-us = <5000>;
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qcom,no-l0s-supported;
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qcom,l1-2-th-scale = <2>;
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qcom,l1-2-th-value = <70>;
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qcom,slv-addr-space-size = <0x4000000>;
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qcom,ep-latency = <10>;
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qcom,num-parf-testbus-sel = <0xb9>;
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qcom,pcie-phy-ver = <10100>;
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qcom,phy-status-offset = <0x214>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x240>;
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qcom,phy-sequence = <0x0240 0x03 0x0
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0x0094 0x08 0x0
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0x0154 0x34 0x0
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0x016c 0x08 0x0
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0x0058 0x0f 0x0
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0x00a4 0x42 0x0
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0x0110 0x24 0x0
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0x011c 0x03 0x0
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0x0118 0xb4 0x0
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0x010c 0x02 0x0
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0x01bc 0x11 0x0
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0x00bc 0x82 0x0
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0x00d4 0x03 0x0
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0x00d0 0x55 0x0
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0x00cc 0x55 0x0
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0x00b0 0x1a 0x0
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0x00ac 0x0a 0x0
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0x00c4 0x68 0x0
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0x00e0 0x02 0x0
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0x00dc 0xaa 0x0
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0x00d8 0xab 0x0
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0x00b8 0x34 0x0
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0x00b4 0x14 0x0
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0x0158 0x01 0x0
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0x0074 0x06 0x0
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0x007c 0x16 0x0
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0x0084 0x36 0x0
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0x0078 0x06 0x0
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0x0080 0x16 0x0
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0x0088 0x36 0x0
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0x01b0 0x1e 0x0
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0x01ac 0xca 0x0
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0x01b8 0x18 0x0
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0x01b4 0xa2 0x0
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0x0050 0x07 0x0
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0x0010 0x01 0x0
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0x001c 0x31 0x0
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0x0020 0x01 0x0
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0x0024 0xde 0x0
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0x0028 0x07 0x0
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0x0030 0x4c 0x0
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0x0034 0x06 0x0
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0x0ee4 0x20 0x0
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0x0e84 0x75 0x0
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0x0e90 0x3f 0x0
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0x115c 0x7f 0x0
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0x1160 0xff 0x0
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0x1164 0xbf 0x0
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0x1168 0x3f 0x0
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0x116c 0xd8 0x0
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0x1170 0xdc 0x0
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0x1174 0xdc 0x0
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0x1178 0x5c 0x0
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0x117c 0x34 0x0
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0x1180 0xa6 0x0
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0x1190 0x34 0x0
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0x10d8 0x07 0x0
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0x0e40 0x0c 0x0
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0x10dc 0x00 0x0
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0x104c 0x08 0x0
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0x1050 0x08 0x0
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0x1044 0xf0 0x0
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0x11a4 0x38 0x0
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0x10cc 0xf0 0x0
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0x0694 0x00 0x0
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0x0654 0x00 0x0
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0x06a8 0x0f 0x0
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0x0044 0x04 0x0
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0x0048 0xf0 0x0
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0x0608 0x0f 0x0
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0x0620 0xc1 0x0
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0x0388 0xa8 0x0
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0x10b0 0x18 0x0
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0x0398 0x0b 0x0
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0x02dc 0x05 0x0
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0x0200 0x00 0x0
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0x0244 0x03 0x0>;
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@17a10040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17a10040 0x0>;
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qcom,msi-addr-size-exp = <20>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
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};
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pcie1: qcom,pcie@1c08000 {
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compatible = "qcom,pci-msm";
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reg = <0x01c08000 0x3000>,
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<0x01c0e000 0x2000>,
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<0x40000000 0xf1d>,
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<0x40000f20 0xa8>,
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<0x40001000 0x1000>,
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<0x40100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
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cell-index = <1>;
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
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interrupt-parent = <&pcie1>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie1_msi>;
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perst-gpio = <&tlmm 97 0>;
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wake-gpio = <&tlmm 99 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_perst_default
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&pcie1_clkreq_default
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&pcie1_wake_default>;
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gdsc-vdd-supply = <&gcc_pcie_1_gdsc>;
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vreg-1p8-supply = <&pm8350_l6>;
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vreg-0p9-supply = <&pm8350_l5>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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qcom,vreg-1p8-voltage-level = <1200000 1200000 25000>;
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qcom,vreg-0p9-voltage-level = <880000 880000 99000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_NOM
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000>;
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interconnect-names = "icc_path";
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interconnects = <&aggre2_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
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clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_PCIE_1_AUX_CLK>,
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<&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>,
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<&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>,
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<&clock_gcc GCC_PCIE_1_CLKREF_EN>,
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<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
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<&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
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<&clock_gcc GCC_PCIE1_PHY_RCHNG_CLK>,
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<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
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<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
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<&clock_gcc GCC_PCIE_1_PIPE_CLK_SRC>,
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<&clock_gcc PCIE_1_PIPE_CLK>;
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clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
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"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
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"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
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"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
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"pcie_tbu_clk", "pcie_phy_refgen_clk",
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"pcie_ddrss_sf_tbu_clk",
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"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
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"pcie_pipe_clk_ext_src";
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max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>, <0>,
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<0>, <0>, <0>;
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resets = <&clock_gcc GCC_PCIE_1_BCR>,
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<&clock_gcc GCC_PCIE_1_PHY_BCR>;
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reset-names = "pcie_1_core_reset",
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"pcie_1_phy_reset";
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dma-coherent;
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qcom,smmu-sid-base = <0x1c80>;
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iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
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<0x100 &apps_smmu 0x1c81 0x1>;
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qcom,boot-option = <0x1>;
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qcom,aux-clk-freq = <20>; /* 19.2 MHz */
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qcom,drv-supported;
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qcom,wr-halt-size = <0x8>;
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qcom,no-l0s-supported;
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qcom,slv-addr-space-size = <0x20000000>;
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qcom,ep-latency = <10>;
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qcom,num-parf-testbus-sel = <0xb9>;
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qcom,pcie-phy-ver = <1106>;
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qcom,phy-status-offset = <0x214>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x240>;
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qcom,phy-sequence = <0x0240 0x03 0x0
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0x0010 0x01 0x0
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0x001c 0x31 0x0
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0x0020 0x01 0x0
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0x0024 0xde 0x0
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0x0028 0x07 0x0
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0x0030 0x4c 0x0
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0x0034 0x06 0x0
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0x0048 0x90 0x0
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0x0058 0x0f 0x0
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0x0074 0x06 0x0
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0x0078 0x06 0x0
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0x007c 0x16 0x0
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0x0080 0x16 0x0
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0x0084 0x36 0x0
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0x0088 0x36 0x0
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0x0094 0x08 0x0
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0x00a4 0x42 0x0
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0x00ac 0x0a 0x0
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0x00b0 0x1a 0x0
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0x00b4 0x14 0x0
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0x00b8 0x34 0x0
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0x00bc 0x82 0x0
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0x00c4 0x68 0x0
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0x00cc 0x55 0x0
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0x00d0 0x55 0x0
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0x00d4 0x03 0x0
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0x00d8 0xab 0x0
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0x00dc 0xaa 0x0
|
|
0x00e0 0x02 0x0
|
|
0x010c 0x02 0x0
|
|
0x0110 0x24 0x0
|
|
0x0118 0xb4 0x0
|
|
0x011c 0x03 0x0
|
|
0x0154 0x34 0x0
|
|
0x0158 0x01 0x0
|
|
0x016c 0x08 0x0
|
|
0x01ac 0xca 0x0
|
|
0x01b0 0x1e 0x0
|
|
0x01b4 0xa2 0x0
|
|
0x01b8 0x18 0x0
|
|
0x01bc 0x11 0x0
|
|
0x0ee4 0x02 0x0
|
|
0x16e4 0x04 0x0
|
|
0x1684 0xd5 0x0
|
|
0x0e84 0xd5 0x0
|
|
0x1690 0x3f 0x0
|
|
0x0e90 0x3f 0x0
|
|
0x115c 0x7f 0x0
|
|
0x1160 0xff 0x0
|
|
0x1164 0x7f 0x0
|
|
0x1168 0x34 0x0
|
|
0x116c 0xd8 0x0
|
|
0x1170 0xdc 0x0
|
|
0x1174 0xdc 0x0
|
|
0x1178 0x5c 0x0
|
|
0x117c 0x34 0x0
|
|
0x1180 0xa6 0x0
|
|
0x195c 0x7f 0x0
|
|
0x1960 0xff 0x0
|
|
0x1964 0x7f 0x0
|
|
0x1968 0x34 0x0
|
|
0x196c 0xd8 0x0
|
|
0x1970 0xdc 0x0
|
|
0x1974 0xdc 0x0
|
|
0x1978 0x5c 0x0
|
|
0x197c 0x34 0x0
|
|
0x1980 0xa6 0x0
|
|
0x10cc 0xf0 0x0
|
|
0x18cc 0xf0 0x0
|
|
0x10d8 0x0f 0x0
|
|
0x18d8 0x0f 0x0
|
|
0x10dc 0x00 0x0
|
|
0x18dc 0x00 0x0
|
|
0x11a4 0x38 0x0
|
|
0x19a4 0x38 0x0
|
|
0x0e3c 0x1d 0x0
|
|
0x163c 0x1d 0x0
|
|
0x0e40 0x0c 0x0
|
|
0x1640 0x0c 0x0
|
|
0x1190 0x34 0x0
|
|
0x1990 0x34 0x0
|
|
0x104c 0x08 0x0
|
|
0x184c 0x08 0x0
|
|
0x1050 0x08 0x0
|
|
0x1850 0x08 0x0
|
|
0x02dc 0x05 0x0
|
|
0x0388 0x77 0x0
|
|
0x0398 0x0b 0x0
|
|
0x03e0 0x0f 0x0
|
|
0x060c 0x1d 0x0
|
|
0x0614 0x07 0x0
|
|
0x0620 0xc1 0x0
|
|
0x0694 0x00 0x0
|
|
0x0200 0x00 0x0
|
|
0x0244 0x03 0x0>;
|
|
|
|
pcie1_rp: pcie1_rp {
|
|
reg = <0 0 0 0 0>;
|
|
};
|
|
};
|
|
|
|
pcie1_msi: qcom,pcie1_msi@17a10040 {
|
|
compatible = "qcom,pci-msi";
|
|
msi-controller;
|
|
reg = <0x17a10040 0x0>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
};
|