mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-25 06:03:36 -04:00
6334e3c800
This change corrects clock nodes for each QUP instance for sdxnightjar. Also correct the interconnect end points for each BLSP QUP instance. Change-Id: I3b3c85b82c23b0e103a2ac11b8c009593dda586a
385 lines
12 KiB
Devicetree
385 lines
12 KiB
Devicetree
#include "sdxnightjar-pinctrl.dtsi"
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/ {
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aliases {
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i2c1 = &i2c_1;
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i2c2 = &i2c_2;
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i2c3 = &i2c_3;
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i2c4 = &i2c_4;
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spi1 = &spi_1;
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spi2 = &spi_2;
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spi3 = &spi_3;
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spi4 = &spi_4;
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};
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};
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&soc {
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dma_blsp1: qcom,sps-dma@0x7884000 { /* BLSP1 */
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#dma-cells = <4>;
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compatible = "qcom,sps-dma";
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reg = <0x7884000 0x23000>;
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interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>;
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qcom,summing-threshold = <0x10>;
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};
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i2c_1: i2c@78b5000 { /* BLSP1 QUP1 gpios 2,3 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "qup_phys_addr";
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reg = <0x78b5000 0x600>;
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interrupt-names = "qup_irq";
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interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
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<&dma_blsp1 9 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <MASTER_BLSP_1>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_1_active>;
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pinctrl-1 = <&i2c_1_sleep>;
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status = "disabled";
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};
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i2c_2: i2c@78B6000 { /* BLSP1 QUP2 gpios 6,7 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "qup_phys_addr";
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reg = <0x78B6000 0x600>;
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interrupt-names = "qup_irq";
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interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
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<&dma_blsp1 11 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <MASTER_BLSP_1>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_2_active>;
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pinctrl-1 = <&i2c_2_sleep>;
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status = "disabled";
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};
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i2c_3: i2c@78B7000 { /* BLSP1 QUP3 gpios 10, 11 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "qup_phys_addr";
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reg = <0x78B7000 0x600>;
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interrupt-names = "qup_irq";
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interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 12 64 0x20000020 0x20>,
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<&dma_blsp1 13 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <MASTER_BLSP_1>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_3_active>;
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pinctrl-1 = <&i2c_3_sleep>;
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status = "disabled";
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};
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i2c_4: i2c@78B8000 { /* BLSP1 QUP4 gpios 14, 15 */
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compatible = "qcom,i2c-msm-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "qup_phys_addr";
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reg = <0x78B8000 0x600>;
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interrupt-names = "qup_irq";
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interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma_blsp1 14 64 0x20000020 0x20>,
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<&dma_blsp1 15 32 0x20000020 0x20>;
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dma-names = "tx", "rx";
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qcom,master-id = <MASTER_BLSP_1>;
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qcom,clk-freq-out = <400000>;
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qcom,clk-freq-in = <19200000>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
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pinctrl-names = "i2c_active", "i2c_sleep";
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pinctrl-0 = <&i2c_4_active>;
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pinctrl-1 = <&i2c_4_sleep>;
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status = "disabled";
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};
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spi_1: spi@78B5000 { /* BLSP1 QUP1 gpios 0, 1, 2, 3 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x078B5000 0x600>,
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<0x7884000 0x23000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>,
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<0 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <19200000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <8>;
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qcom,bam-producer-pipe-index = <9>;
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qcom,master-id = <MASTER_BLSP_1>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_1_active>;
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pinctrl-1 = <&spi_1_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_2: spi@78B6000 { /* BLSP1 QUP2 gpios 4, 5, 6, 7 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x78B6000 0x600>,
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<0x7884000 0x23000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>,
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<0 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <19200000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <10>;
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qcom,bam-producer-pipe-index = <11>;
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qcom,master-id = <MASTER_BLSP_1>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_2_active>;
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pinctrl-1 = <&spi_2_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_3: spi@78B7000 { /* BLSP1 QUP3 gpios 8, 9, 10, 11 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x078B7000 0x600>,
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<0x7884000 0x23000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>,
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<0 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <19200000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <12>;
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qcom,bam-producer-pipe-index = <13>;
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qcom,master-id = <MASTER_BLSP_1>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_3_active>;
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pinctrl-1 = <&spi_3_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
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status = "disabled";
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};
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spi_4: spi@78B8000 { /* BLSP1 QUP4 gpios 16, 17, 18, 19 */
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compatible = "qcom,spi-qup-v2";
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#address-cells = <1>;
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#size-cells = <0>;
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reg-names = "spi_physical", "spi_bam_physical";
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reg = <0x078B8000 0x600>,
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<0x7884000 0x23000>;
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interrupt-names = "spi_irq", "spi_bam_irq";
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interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>,
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<0 238 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <19200000>;
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qcom,use-bam;
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qcom,ver-reg-exists;
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qcom,bam-consumer-pipe-index = <14>;
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qcom,bam-producer-pipe-index = <15>;
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qcom,master-id = <MASTER_BLSP_1>;
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qcom,use-pinctrl;
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pinctrl-names = "spi_default", "spi_sleep";
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pinctrl-0 = <&spi_4_active>;
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pinctrl-1 = <&spi_4_sleep>;
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clock-names = "iface_clk", "core_clk";
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
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status = "disabled";
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};
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blsp1_uart1_hs: uart@78AF000 { /* BLSP1 UART1 gpios 0, 1, 2, 3 */
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compatible = "qcom,msm-hsuart-v14";
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reg = <0x78AF000 0x200>,
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<0x7884000 0x23000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&blsp1_uart1_hs>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 107 IRQ_TYPE_LEVEL_HIGH
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1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH
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2 &tlmm_pinmux 1 IRQ_TYPE_LEVEL_HIGH>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xFD>;
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qcom,bam-tx-ep-pipe-index = <0>;
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qcom,bam-rx-ep-pipe-index = <1>;
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qcom,master-id = <86>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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pinctrl-names = "sleep", "default";
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pinctrl-0 = <&blsp1_uart1_sleep>;
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pinctrl-1 = <&blsp1_uart1_active>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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status = "disabled";
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};
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blsp1_uart2_hs: uart@78B0000 { /* BLSP1 UART2 gpios 4, 5, 6, 7 */
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compatible = "qcom,msm-hsuart-v14";
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reg = <0x78B0000 0x200>,
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<0x7884000 0x23000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&blsp1_uart2_hs>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 108 IRQ_TYPE_LEVEL_HIGH
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1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH
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2 &tlmm_pinmux 5 IRQ_TYPE_LEVEL_HIGH>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xFD>;
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qcom,bam-tx-ep-pipe-index = <2>;
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qcom,bam-rx-ep-pipe-index = <3>;
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qcom,master-id = <86>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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pinctrl-names = "sleep", "default";
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pinctrl-0 = <&blsp1_uart2_sleep>;
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pinctrl-1 = <&blsp1_uart2_active>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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status = "disabled";
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};
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blsp1_uart3_hs: uart@78B1000 { /* BLSP1 UART3 gpios 8, 9, 10, 11 */
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compatible = "qcom,msm-hsuart-v14";
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reg = <0x78B1000 0x200>,
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<0x7884000 0x23000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&blsp1_uart3_hs>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 109 IRQ_TYPE_LEVEL_HIGH
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1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH
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2 &tlmm_pinmux 9 IRQ_TYPE_LEVEL_HIGH>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xFD>;
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qcom,bam-tx-ep-pipe-index = <4>;
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qcom,bam-rx-ep-pipe-index = <5>;
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qcom,master-id = <86>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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pinctrl-names = "sleep", "default";
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pinctrl-0 = <&blsp1_uart3_sleep>;
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pinctrl-1 = <&blsp1_uart3_active>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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status = "disabled";
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};
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blsp1_uart4a_hs: uarta@78B2000 { /* BLSP1 UART4 gpios 12, 13, 14, 15*/
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compatible = "qcom,msm-hsuart-v14";
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reg = <0x78B2000 0x200>,
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<0x7884000 0x23000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&blsp1_uart4a_hs>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 110 IRQ_TYPE_LEVEL_HIGH
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1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH
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2 &tlmm_pinmux 13 IRQ_TYPE_LEVEL_HIGH>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xFD>;
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qcom,bam-tx-ep-pipe-index = <6>;
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qcom,bam-rx-ep-pipe-index = <7>;
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qcom,master-id = <86>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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pinctrl-names = "sleep", "default";
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pinctrl-0 = <&blsp1_uart4_sleep>;
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pinctrl-1 = <&blsp1_uart4_active>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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status = "disabled";
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};
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blsp1_uart4b_hs: uartb@78B2000 { /* BLSP1 UART4b gpios 16, 17, 18, 19*/
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compatible = "qcom,msm-hsuart-v14";
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reg = <0x78B2000 0x200>,
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<0x7884000 0x23000>;
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reg-names = "core_mem", "bam_mem";
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interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
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#address-cells = <0>;
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interrupt-parent = <&blsp1_uart4b_hs>;
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interrupts = <0 1 2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc 0 110 IRQ_TYPE_LEVEL_HIGH
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1 &intc 0 238 IRQ_TYPE_LEVEL_HIGH
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2 &tlmm_pinmux 17 IRQ_TYPE_LEVEL_HIGH>;
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qcom,inject-rx-on-wakeup;
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qcom,rx-char-to-inject = <0xFD>;
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qcom,bam-tx-ep-pipe-index = <6>;
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qcom,bam-rx-ep-pipe-index = <7>;
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qcom,master-id = <86>;
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clock-names = "core_clk", "iface_clk";
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clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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pinctrl-names = "sleep", "default";
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pinctrl-0 = <&blsp1_uart4b_sleep>;
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pinctrl-1 = <&blsp1_uart4b_active>;
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interconnect-names = "blsp-ddr";
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interconnects = <&pc_noc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>;
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status = "disabled";
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};
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};
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