mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-12 01:51:34 -05:00
3d53a281f3
Add initial device tree support for monaco target on rumi platform. Update the bindings for same. Change-Id: I6542a62d89cd07dd3495988ec2670f6f695c8470
389 lines
7.3 KiB
Devicetree
389 lines
7.3 KiB
Devicetree
#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm Technologies, Inc. Monaco";
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compatible = "qcom,monaco";
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qcom,msm-id = <459 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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next-level-cache = <&L2_0>;
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L1_I_1: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_1: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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next-level-cache = <&L2_0>;
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L1_I_2: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_2: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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CPU3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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next-level-cache = <&L2_0>;
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L1_I_3: l1-icache {
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compatible = "arm,arch-cache";
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};
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L1_D_3: l1-dcache {
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compatible = "arm,arch-cache";
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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soc: soc { };
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chosen {
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bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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#gpio-cells = <2>;
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compatible = "simple-bus";
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intc: interrupt-controller@f200000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0xf200000 0x10000>, /* GICD */
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<0xf300000 0x80000>; /* GICR * 4 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@f120000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x0f120000 0x1000>;
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clock-frequency = <19200000>;
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frame@f121000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x0f121000 0x1000>,
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<0x0f122000 0x1000>;
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};
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frame@f123000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf123000 0x1000>;
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status = "disabled";
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};
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frame@f124000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf124000 0x1000>;
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status = "disabled";
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};
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frame@f125000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf125000 0x1000>;
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status = "disabled";
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};
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frame@f126000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf126000 0x1000>;
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status = "disabled";
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};
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frame@f127000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf127000 0x1000>;
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status = "disabled";
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};
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frame@f128000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf128000 0x1000>;
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status = "disabled";
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};
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};
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qcom,msm-imem@c125000 {
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compatible = "qcom,msm-imem";
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reg = <0xc125000 0x1000>;
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ranges = <0x0 0xc125000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mem_dump_table@10 {
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compatible = "qcom,msm-imem-mem_dump_table";
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reg = <0x10 0x8>;
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};
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restart_reason@65c {
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compatible = "qcom,msm-imem-restart_reason";
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reg = <0x65c 0x4>;
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};
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dload_type@1c {
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compatible = "qcom,msm-imem-dload-type";
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reg = <0x1c 0x4>;
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};
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boot_stats@6b0 {
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compatible = "qcom,msm-imem-boot_stats";
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reg = <0x6b0 0x20>;
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};
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kaslr_offset@6d0 {
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compatible = "qcom,msm-imem-kaslr_offset";
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reg = <0x6d0 0xc>;
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};
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pil@94c {
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compatible = "qcom,msm-imem-pil";
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reg = <0x94c 0xc8>;
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};
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diag_dload@c8 {
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compatible = "qcom,msm-imem-diag-dload";
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reg = <0xc8 0xc8>;
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};
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};
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restart@440b000 {
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compatible = "qcom,pshold";
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reg = <0x440b000 0x4>, <0x03d3000 0x4>;
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reg-names = "pshold-base", "tcsr-boot-misc-detect";
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};
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qcom,mpm2-slepp-counter@4403000 {
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compatible = "qcom,mpm2-sleep-counter";
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reg = <0x4403000 0x1000>;
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clock-frequency = <32768>;
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};
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qcom,msm-rtb {
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compatible = "qcom,msm-rtb";
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qcom,rtb-size = <0x100000>;
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};
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qcom,chd_silver {
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compatible = "qcom,core-hang-detect";
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label = "silver";
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qcom,threshold-arr = <0x0f1880b0 0x0f1980b0
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0x0f1a80b0 0x0f1b80b0>;
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qcom,config-arr = <0x0f1880b8 0x0f1980b8
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0x0f1a80b8 0x0f1b80b8>;
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};
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wdog: qcom,wdt@f017000 {
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compatible = "qcom,msm-watchdog";
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reg = <0xf017000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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qcom,bark-time = <11000>;
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qcom,pet-time = <9360>;
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qcom,ipi-ping;
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qcom,wakeup-enable;
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};
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qfprom: qfprom@1b40000 {
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compatible = "qcom,qfprom";
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reg = <0x1b40000 0x7000>;
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#address-cells = <1>;
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#size-cells = <1>;
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read-only;
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ranges;
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};
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mem_dump {
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compatible = "qcom,mem-dump";
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c0_context {
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qcom,dump-size = <0x800>;
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qcom,dump-id = <0x0>;
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};
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c1_context {
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qcom,dump-size = <0x800>;
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qcom,dump-id = <0x1>;
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};
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c2_context {
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qcom,dump-size = <0x800>;
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qcom,dump-id = <0x2>;
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};
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c3_context {
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qcom,dump-size = <0x800>;
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qcom,dump-id = <0x3>;
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};
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l1_icache0 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x60>;
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};
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l1_icache1 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x61>;
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};
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l1_icache2 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x62>;
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};
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l1_icache3 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x63>;
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};
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l1_dcache0 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x80>;
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};
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l1_dcache1 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x81>;
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};
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l1_dcache2 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x82>;
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};
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l1_dcache3 {
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qcom,dump-size = <0x9040>;
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qcom,dump-id = <0x83>;
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};
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l2_tlb0 {
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qcom,dump-size = <0x2000>;
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qcom,dump-id = <0x120>;
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};
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l2_tlb1 {
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qcom,dump-size = <0x2000>;
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qcom,dump-id = <0x121>;
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};
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l2_tlb2 {
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qcom,dump-size = <0x2000>;
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qcom,dump-id = <0x122>;
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};
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l2_tlb3 {
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qcom,dump-size = <0x2000>;
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qcom,dump-id = <0x123>;
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};
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};
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};
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#include "monaco-pinctrl.dtsi"
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