mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-12 01:51:34 -05:00
766b8be48c
Add support for pinctrl node for SA8195 platform. Change-Id: Ie23e29845ecaad9588b32d67ed7d47b9bbcf5062
656 lines
13 KiB
Devicetree
656 lines
13 KiB
Devicetree
#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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model = "Qualcomm Technologies, Inc. SDMSHRIKE";
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compatible = "qcom,sdmshrike";
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qcom,msm-name = "SDMSHRIKE";
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qcom,msm-id = <340 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases {
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serial0 = &uart2;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_0>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x400000>;
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cache-level = <3>;
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};
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_1>;
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#cooling-cells = <2>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_100: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_D_100: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_2>;
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#cooling-cells = <2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_200: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_D_200: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_3>;
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#cooling-cells = <2>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_300: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_D_300: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x400>;
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enable-method = "psci";
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capacity-dmips-mhz = <1740>;
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cache-size = <0x20000>;
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next-level-cache = <&L2_4>;
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#cooling-cells = <2>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_400: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_D_400: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x500>;
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enable-method = "psci";
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capacity-dmips-mhz = <1740>;
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cache-size = <0x20000>;
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next-level-cache = <&L2_5>;
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#cooling-cells = <2>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_500: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_D_500: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x600>;
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enable-method = "psci";
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capacity-dmips-mhz = <1740>;
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cache-size = <0x20000>;
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next-level-cache = <&L2_6>;
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#cooling-cells = <2>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_600: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_D_600: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x700>;
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enable-method = "psci";
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capacity-dmips-mhz = <1740>;
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cache-size = <0x20000>;
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next-level-cache = <&L2_7>;
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#cooling-cells = <2>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_700: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_D_700: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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firmware: firmware {
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: hyp_mem@85700000 {
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no-map;
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reg = <0x0 0x85700000 0x0 0x600000>;
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};
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xbl_aop_mem: xbl_aop_mem@85e00000 {
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no-map;
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reg = <0x0 0x85e00000 0x0 0x140000>;
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};
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flex_sec_apps_mem: flex_sec_apps_regions@85ffd000 {
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no-map;
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reg = <0x0 0x85ffd000 0x0 0x3000>;
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};
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smem_region: smem@86000000 {
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no-map;
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reg = <0x0 0x86000000 0x0 0x200000>;
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};
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removed_regions: removed_regions@86200000 {
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no-map;
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reg = <0x0 0x86200000 0x0 0x5500000>;
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};
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pil_camera_mem: camera_region@8b700000 {
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no-map;
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reg = <0x0 0x8b700000 0x0 0x500000>;
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};
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pil_wlan_fw_mem: pil_wlan_fw_region@8bc00000 {
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no-map;
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reg = <0x0 0x8bc00000 0x0 0x180000>;
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};
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pil_npu_mem: pil_npu_region@0x8bd80000 {
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no-map;
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reg = <0x0 0x8bd80000 0x0 0x80000>;
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};
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pil_adsp_mem: pil_adsp_region@0x8be00000 {
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no-map;
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reg = <0x0 0x8be00000 0x0 0x1a00000>;
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};
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pil_modem_mem: modem_region@0x8d800000 {
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no-map;
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reg = <0x0 0x8d800000 0x0 0x9600000>;
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};
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pil_video_mem: pil_video_region@0x96e00000 {
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no-map;
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reg = <0x0 0x96e00000 0x0 0x500000>;
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};
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pil_slpi_mem: pil_slpi_region@0x97300000 {
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no-map;
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reg = <0x0 0x97300000 0x0 0x1400000>;
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};
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pil_ipa_fw_mem: pil_ipa_fw_region@0x98700000 {
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no-map;
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reg = <0x0 0x98700000 0x0 0x10000>;
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};
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pil_ipa_gsi_mem: pil_ipa_gsi_region@0x98710000 {
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no-map;
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reg = <0x0 0x98710000 0x0 0x5000>;
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};
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pil_gpu_mem: pil_gpu_region@0x98715000 {
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no-map;
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reg = <0x0 0x98715000 0x0 0x2000>;
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};
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pil_spss_mem: pil_spss_region@0x98800000 {
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no-map;
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reg = <0x0 0x98800000 0x0 0x100000>;
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};
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pil_cdsp_mem: cdsp_regions@0x98900000 {
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no-map;
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reg = <0x0 0x98900000 0x0 0x1400000>;
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};
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qseecom_mem: qseecom_region@0x9e400000 {
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compatible = "shared-dma-pool";
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no-map;
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reg = <0x0 0x9e400000 0x0 0x1400000>;
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};
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cont_splash_memory: cont_splash_region@0x9c000000 {
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reg = <0x0 0x9c000000 0x0 0x02400000>;
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label = "cont_splash_region";
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};
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disp_rdump_memory: disp_rdump_region@0x9c000000 {
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reg = <0x0 0x9c000000 0x0 0x02400000>;
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label = "disp_rdump_region";
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};
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adsp_mem: adsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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cdsp_mem: cdsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x400000>;
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};
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user_contig_mem: user_contig_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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qseecom_ta_mem: qseecom_ta_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x800000>;
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};
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secure_display_memory: secure_display_region { /* Secure UI */
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0xA000000>;
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};
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dump_mem: mem_dump_region {
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compatible = "shared-dma-pool";
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reusable;
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size = <0 0x2400000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2800000>;
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linux,cma-default;
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};
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};
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vendor: vendor {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17a00000 0x10000>, /* GICD */
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<0x17a60000 0x100000>; /* GICR * 8 */
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interrupts = <1 9 4>;
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interrupt-parent = <&intc>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 1 0xf08>,
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<1 2 0xf08>,
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<1 3 0xf08>,
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<1 0 0xf08>;
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clock-frequency = <19200000>;
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};
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timer@0x17c20000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17c20000 0x1000>;
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clock-frequency = <19200000>;
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frame@0x17c21000 {
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frame-number = <0>;
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interrupts = <0 7 0x4>,
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<0 6 0x4>;
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reg = <0x17c21000 0x1000>,
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<0x17c22000 0x1000>;
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};
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frame@17c23000 {
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frame-number = <1>;
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interrupts = <0 8 0x4>;
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reg = <0x17c23000 0x1000>;
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status = "disabled";
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};
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frame@17c25000 {
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frame-number = <2>;
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interrupts = <0 9 0x4>;
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reg = <0x17c25000 0x1000>;
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status = "disabled";
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};
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frame@17c27000 {
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frame-number = <3>;
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interrupts = <0 10 0x4>;
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reg = <0x17c26000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c29000 {
|
|
frame-number = <4>;
|
|
interrupts = <0 11 0x4>;
|
|
reg = <0x17c29000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
frame-number = <5>;
|
|
interrupts = <0 12 0x4>;
|
|
reg = <0x17c2b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
frame-number = <6>;
|
|
interrupts = <0 13 0x4>;
|
|
reg = <0x17c2d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qcom,msm-imem@146bf000 {
|
|
compatible = "qcom,msm-imem";
|
|
reg = <0x146bf000 0x1000>;
|
|
ranges = <0x0 0x146bf000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x8>;
|
|
};
|
|
|
|
restart_reason@65c {
|
|
compatible = "qcom,msm-imem-restart_reason";
|
|
reg = <0x65c 0x4>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x4>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0xc>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,msm-imem-pil";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
};
|
|
|
|
qcom,msm-rtb {
|
|
compatible = "qcom,msm-rtb";
|
|
qcom,rtb-size = <0x100000>;
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@c221000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0xc221000 0x1000>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x18200000 0x10000>,
|
|
<0x18210000 0x10000>,
|
|
<0x18220000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 1>,
|
|
<WAKE_TCS 1>,
|
|
<CONTROL_TCS 0>;
|
|
|
|
};
|
|
|
|
qupv3_id_1: geniqup@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x00ac0000 0x6000>;
|
|
ranges;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
status = "disabled";
|
|
|
|
uart2: serial@a90000 {
|
|
compatible = "qcom,geni-debug-uart";
|
|
reg = <0x0 0x00a90000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "ok"
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
#include "sdmshrike-pinctrl.dtsi"
|