mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-12 01:51:34 -05:00
c1f6098935
Add pmd9650 nodes and include pmic devicetree files in target specific files. Change-Id: Ia19f577dc8a295dabd20ce4089dca553b9e881e8
432 lines
9.3 KiB
Devicetree
432 lines
9.3 KiB
Devicetree
#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Qualcomm Technologies, Inc. SDXNIGHTJAR";
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compatible = "qcom,sdxnightjar";
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qcom,msm-id = <484 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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chosen { };
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memory {
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device_type = "memory";
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reg = <0 0>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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peripheral1_mem: peripheral1_region@0x87800000 {
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no-map;
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reg = <0x87800000 0x400000>;
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label = "peripheral1_mem";
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};
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peripheral2_mem: peripheral2_region@0x87d00000 {
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no-map;
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reg = <0x87d00000 0x300000>;
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label = "peripheral2_mem";
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};
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};
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aliases { };
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cpus {
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#size-cells = <0>;
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#address-cells = <1>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x0b000000 0x1000>,
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<0x0b002000 0x1000>;
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};
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qcom,mpm2-sleep-counter@4a3000 {
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compatible = "qcom,mpm2-sleep-counter";
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reg = <0x004a3000 0x1000>;
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clock-frequency = <32768>;
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};
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qcom,msm-imem@8600000 {
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compatible = "qcom,msm-imem";
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reg = <0x8600000 0x1000>; /* Address and size of IMEM */
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ranges = <0x0 0x8600000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mem_dump_table@10 {
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compatible = "qcom,msm-imem-mem_dump_table";
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reg = <0x10 0x8>;
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};
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restart_reason@65c {
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compatible = "qcom,msm-imem-restart_reason";
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reg = <0x65c 0x4>;
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};
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boot_stats@6b0 {
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compatible = "qcom,msm-imem-boot_stats";
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reg = <0x6b0 0x20>;
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};
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pil@94c {
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compatible = "qcom,msm-imem-pil";
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reg = <0x94c 0xc8>;
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};
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};
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clock_gcc: qcom,gcc@1800000 {
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ompatible = "qcom,dummycc";
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#clock-cells = <1>;
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};
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clock_debug: qcom,cc-debug@1874000 {
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compatible = "qcom,dummycc";
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#clock-cells = <1>;
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};
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clock_cpu: qcom,clock-a7@0b010008 {
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compatible = "qcom,dummycc";
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#clock-cells = <1>;
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};
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qcom,msm-cpufreq {
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compatible = "qcom,msm-cpufreq";
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/*TODO: Fix the clock when tree is available*/
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clock-names = "cpu0_clk", "cpu1_clk",
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"cpu2_clk", "cpu3_clk";
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qcom,cpufreq-table =
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< 200000 >,
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< 300000 >,
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< 384000 >,
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< 600000 >,
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< 787200 >,
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< 998400 >,
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< 1190400 >,
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< 1286400 >;
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};
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ahb_clk: qcom,ahb-clk-src {
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compatible = "devfreq-simple-dev";
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clock-names = "devfreq_clk";
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/*TODO: Fix the clock when tree is available*/
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governor = "powersave";
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freq-tbl-khz =
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< 19200 >,
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< 50000 >,
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< 100000 >,
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< 133330 >;
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};
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restart@4ab000 {
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compatible = "qcom,pshold";
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reg = <0x4ab000 0x4>,
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<0x0193d100 0x4>;
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reg-names = "pshold-base", "tcsr-boot-misc-detect";
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};
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timer@b020000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0xb020000 0x1000>;
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clock-frequency = <19200000>;
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frame@b021000 {
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frame-number = <0>;
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interrupts = <0 7 0x4>,
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<0 6 0x4>;
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reg = <0xb021000 0x1000>,
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<0xb022000 0x1000>;
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};
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frame@b023000 {
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frame-number = <1>;
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interrupts = <0 8 0x4>;
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reg = <0xb023000 0x1000>;
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status = "disabled";
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};
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frame@b024000 {
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frame-number = <2>;
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interrupts = <0 9 0x4>;
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reg = <0xb024000 0x1000>;
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status = "disabled";
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};
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frame@b025000 {
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frame-number = <3>;
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interrupts = <0 10 0x4>;
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reg = <0xb025000 0x1000>;
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status = "disabled";
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};
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frame@b026000 {
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frame-number = <4>;
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interrupts = <0 11 0x4>;
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reg = <0xb026000 0x1000>;
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status = "disabled";
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};
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frame@b027000 {
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frame-number = <5>;
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interrupts = <0 12 0x4>;
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reg = <0xb027000 0x1000>;
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status = "disabled";
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};
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frame@b028000 {
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frame-number = <6>;
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interrupts = <0 13 0x4>;
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reg = <0xb028000 0x1000>;
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status = "disabled";
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};
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frame@b029000 {
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frame-number = <7>;
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interrupts = <0 14 0x4>;
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reg = <0xb029000 0x1000>;
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status = "disabled";
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};
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};
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qcom,msm_gsi {
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compatible = "qcom,msm_gsi";
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};
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qcom_rng: qrng@e3000 {
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compatible = "qcom,msm-rng";
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reg = <0xe3000 0x1000>;
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qcom,msm-rng-iface-clk;
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qcom,no-qrng-config;
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qcom,msm-bus,name = "msm-rng-noc";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<1 618 0 0>, /* No vote */
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<1 618 0 800>; /* 100 MB/s */
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/*TODO: Fix the clock when tree is available*/
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clock-names = "iface_clk";
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};
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qcom_tzlog: tz-log@08600720 {
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compatible = "qcom,tz-log";
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reg = <0x08600720 0x2000>;
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};
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qcom,qcedev@720000 {
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compatible = "qcom,qcedev";
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reg = <0x720000 0x20000>,
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<0x704000 0x20000>;
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reg-names = "crypto-base","crypto-bam-base";
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interrupts = <0 207 0>;
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qcom,bam-pipe-pair = <1>;
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qcom,ce-hw-instance = <0>;
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qcom,ce-device = <0>;
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qcom,ce-hw-shared;
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qcom,msm-bus,name = "qcedev-noc";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<47 512 0 0>,
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<47 512 393600 393600>;
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/*TODO: Fix the clock when tree is available*/
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clock-names = "core_clk", "iface_clk",
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"bus_clk","core_clk_src";
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qcom,ce-opp-freq = <171430000>;
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};
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qcom,qcrypto@720000 {
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compatible = "qcom,qcrypto";
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reg = <0x720000 0x20000>,
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<0x704000 0x20000>;
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reg-names = "crypto-base","crypto-bam-base";
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interrupts = <0 207 0>;
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qcom,bam-pipe-pair = <2>;
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qcom,ce-hw-instance = <0>;
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qcom,ce-device = <0>;
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qcom,ce-hw-shared;
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qcom,msm-bus,name = "qcrypto-noc";
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qcom,msm-bus,num-cases = <2>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<47 512 0 0>,
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<47 512 393600 393600>;
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/*TODO: Fix the clock when tree is available*/
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clock-names = "core_clk", "iface_clk",
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"bus_clk","core_clk_src";
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qcom,use-sw-aes-cbc-ecb-ctr-algo;
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qcom,use-sw-aes-xts-algo;
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qcom,use-sw-aes-ccm-algo;
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qcom,use-sw-ahash-algo;
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qcom,use-sw-hmac-algo;
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qcom,use-sw-aead-algo;
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qcom,ce-opp-freq = <171430000>;
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};
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qcom_seecom: qseecom@87800000 {
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compatible = "qcom,qseecom";
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reg = <0x87800000 0x200000>;
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reg-names = "secapp-region";
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qcom,hlos-ce-hw-instance = <0>;
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qcom,qsee-ce-hw-instance = <0>;
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qcom,msm-bus,name = "qseecom-noc";
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qcom,msm-bus,num-cases = <4>;
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qcom,msm-bus,num-paths = <1>;
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qcom,msm-bus,vectors-KBps =
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<47 512 0 0>,
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<47 512 200000 400000>,
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<47 512 300000 800000>,
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<47 512 400000 1000000>;
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/*TODO: Fix the clock when tree is available*/
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clock-names = "core_clk", "iface_clk",
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"bus_clk","core_clk_src";
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qcom,ce-opp-freq = <100000000>;
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};
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qcom,rmnet-ipa {
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compatible = "qcom,rmnet-ipa3";
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qcom,rmnet-ipa-ssr;
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};
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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interrupts = <0 107 0>;
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/*TODO: Fix the clock when tree is available*/
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_uart2: serial@78b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b0000 0x200>;
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interrupts = <0 108 0>;
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/*TODO: Fix the clock when tree is available*/
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clock-names = "core", "iface";
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status = "disabled";
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};
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blsp1_uart3: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b1000 0x200>;
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interrupts = <0 109 0>;
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/*TODO: Fix the clock when tree is available*/
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clock-names = "core", "iface";
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status = "disabled";
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};
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rpm_bus: qcom,rpm-smd {
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compatible = "qcom,rpm-smd";
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rpm-channel-name = "rpm_requests";
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rpm-channel-type = <15>; /* SMD_APPS_RPM */
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};
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qcom,wdt@b017000 {
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compatible = "qcom,msm-watchdog";
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reg = <0xb017000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <1 3 0>, <1 2 0>;
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qcom,bark-time = <11000>;
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qcom,pet-time = <10000>;
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};
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qcom,msm-rtb {
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compatible = "qcom,msm-rtb";
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qcom,rtb-size = <0x100000>;
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};
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jtag_mm0: jtagmm@842000 {
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compatible = "qcom,jtag-mm";
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reg = <0x842000 0x1000>,
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<0x840000 0x1000>;
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reg-names = "etm-base","debug-base";
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qcom,coresight-jtagmm-cpu = <&CPU0>;
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/*TODO: Fix the clock when tree is available*/
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clock-names = "core_clk", "core_a_clk";
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};
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qcom,smem@87e80000 {
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compatible = "qcom,smem";
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reg = <0x87e80000 0xc0000>,
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<0xb011008 0x4>,
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<0x60000 0x6000>,
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<0x193d000 0x8>;
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reg-names = "smem", "irq-reg-base", "aux-mem1",
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"smem_targ_info_reg";
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qcom,mpu-enabled;
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qcom,smd-modem {
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compatible = "qcom,smd";
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qcom,smd-edge = <0>;
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qcom,smd-irq-offset = <0x0>;
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qcom,smd-irq-bitmask = <0x1000>;
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interrupts = <0 25 1>;
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label = "modem";
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};
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qcom,smd-rpm {
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compatible = "qcom,smd";
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qcom,smd-edge = <15>;
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qcom,smd-irq-offset = <0x0>;
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qcom,smd-irq-bitmask = <0x1>;
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interrupts = <0 168 1>;
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label = "rpm";
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qcom,irq-no-suspend;
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qcom,not-loadable;
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};
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};
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spmi_bus: qcom,spmi@200f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x200f000 0x1000>,
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<0x2400000 0x800000>,
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<0x2c00000 0x800000>,
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<0x3800000 0x200000>,
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<0x200a000 0x2100>; /* includes SPMI_CFG and GENI_CFG */
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reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
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interrupts = <0 190 0>;
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qcom,pmic-arb-channel = <0>;
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qcom,pmic-arb-ee = <0>;
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qcom,pmic-arb-max-peripherals = <256>;
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qcom,pmic-arb-max-periph-interrupts = <256>;
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#interrupt-cells = <3>;
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interrupt-controller;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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};
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};
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#include "pmd9650.dtsi"
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#include "pmd9650-rpm-regulator.dtsi"
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#include "sdxnightjar-regulator.dtsi"
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#include "sdxnightjar-pinctrl.dtsi"
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