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android_kernel_motorola_sm6375/qcom/shima.dtsi
Vaibhav Agrawal fa0123c586 ARM: dts: msm: Add the hwkm ice slave regions to storage node 
The HWKM ICE slave memory regions are different for UFS and
EMMC storage type. We parse the values in the storage related
drivers now hence adding the memory regions to the corresponding
storage driver dtsi nodes for holi, shima and lahaina.

Change-Id: I5bec8a164f3b947d5d6ef6fcfc384624b1fa58ca
2020-11-10 06:52:09 -08:00

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#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,camcc-shima.h>
#include <dt-bindings/clock/qcom,dispcc-shima.h>
#include <dt-bindings/clock/qcom,gcc-shima.h>
#include <dt-bindings/clock/qcom,gpucc-shima.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-shima.h>
#include <dt-bindings/interconnect/qcom,epss-l3.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,shima.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
opp-supported-hw = <ddrtype>;}
#define DDR_TYPE_LPDDR4X 7
#define DDR_TYPE_LPDDR5 8
/ {
model = "Qualcomm Technologies, Inc. Shima";
compatible = "qcom,shima";
qcom,msm-id = <450 0x10000>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
mem-offline {
compatible = "qcom,mem-offline";
offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
<0x1 0xc0000000 0x0 0x80000000>,
<0x2 0xc0000000 0x1 0x40000000>;
granule = <512>;
mboxes = <&qmp_aop 0>;
};
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
sdhc1 = &sdhc_1; /*SDC1 eMMC slot*/
sdhc2 = &sdhc_2; /* SDC2 SD card slot */
swr0 = &swr0;
swr1 = &swr1;
swr2 = &swr2;
serial0 = &qupv3_se13_2uart;
hsuart0 = &qupv3_se15_4uart;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-level = <3>;
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0 4>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
next-level-cache = <&L2_3>;
#cooling-cells = <2>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
next-level-cache = <&L2_4>;
#cooling-cells = <2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
next-level-cache = <&L2_5>;
#cooling-cells = <2>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1 4>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
next-level-cache = <&L2_6>;
#cooling-cells = <2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 2 4>;
capacity-dmips-mhz = <1985>;
dynamic-power-coefficient = <552>;
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
next-level-cache = <&L2_7>;
#cooling-cells = <2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
};
cluster2 {
core0 {
cpu = <&CPU7>;
};
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: hyp@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0x600000>;
};
xbl_aop_mem: xbl_aop_mem@80700000 {
no-map;
reg = <0x0 0x80700000 0x0 0x160000>;
};
cmd_db: reserved-memory@80860000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x0 0x80860000 0x0 0x20000>;
};
reserved_xbl_uefi: reserved_xbl_uefi@80880000 {
no-map;
reg = <0x0 0x80880000 0x0 0x14000>;
};
smem_mem: smem@80900000 {
no-map;
reg = <0x0 0x80900000 0x0 0x200000>;
};
fw_mem: fw_mem@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
cdsp_secure_heap_mem: cdsp_secure_heap_mem@80c00000 {
no-map;
reg = <0x0 0x80c00000 0x0 0x4600000>;
};
pil_camera_mem: camera@85800000 {
no-map;
reg = <0x0 0x85800000 0x0 0x500000>;
};
pil_video_mem: video@85d00000 {
no-map;
reg = <0x0 0x85d00000 0x0 0x500000>;
};
pil_cvp_mem: cvp@86200000 {
no-map;
reg = <0x0 0x86200000 0x0 0x500000>;
};
pil_adsp_mem: adsp@86700000 {
no-map;
reg = <0x0 0x86700000 0x0 0x2800000>;
};
pil_cdsp_mem: cdsp@88f00000 {
no-map;
reg = <0x0 0x88f00000 0x0 0x1e00000>;
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xC00000>;
};
pil_wlan_mem: wlan@8ad00000 {
no-map;
reg = <0x0 0x8ad00000 0x0 0xa00000>;
};
pil_ipa_fw_mem: ipa_fw@8b700000 {
no-map;
reg = <0x0 0x8b700000 0x0 0x10000>;
};
pil_ipa_gsi_mem: ipa_gsi@8b710000 {
no-map;
reg = <0x0 0x8b710000 0x0 0xa000>;
};
pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 {
no-map;
reg = <0x0 0x8b71a000 0x0 0x2000>;
};
pil_mpss_wlan_mem: mpss_wlan@8b800000 {
no-map;
reg = <0x0 0x8b800000 0x0 0x10000000>;
};
removed_mem: removed_region@c0000000 {
no-map;
reg = <0x0 0xc0000000 0x0 0x5100000>;
};
pil_trustedvm_mem: pil_trustedvm_region@d0800000 {
no-map;
reg = <0x0 0xd0800000 0x0 0x76f7000>;
};
qrtr_shbuf: qrtr-shmem {
no-map;
reg = <0x0 0xd7ef7000 0x0 0x9000>;
};
chan0_shbuf: neuron_block@0 {
no-map;
reg = <0x0 0xd7f00000 0x0 0x80000>;
};
chan1_shbuf: neuron_block@1 {
no-map;
reg = <0x0 0xd7f80000 0x0 0x80000>;
};
user_contig_mem: user_contig_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
secure_display_memory: secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0xA000000>;
};
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
qcom: ramoops {
compatible = "ramoops";
reg = <0x0 0xa9000000 0x0 0x200000>;
pmsg-size = <0x200000>;
mem-type = <2>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
linux,cma-default;
};
cdsp_mem: cdsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x400000>;
};
memshare_mem: memshare_region {
compatible = "shared-dma-pool";
no-map;
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
alignment = <0x0 0x100000>;
size = <0x0 0x800000>;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
size = <0 0x2c00000>;
};
audio_cma_mem: audio_cma_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1C00000>;
};
splash_memory: splash_region {
reg = <0x0 0xe1000000 0x0 0x02300000>;
label = "cont_splash_region";
};
dfps_data_memory: dfps_data_memory {
reg = <0x0 0xe3300000 0x0 0x0100000>;
label = "dfps_data_memory";
};
non_secure_display_memory: non_secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x6400000>;
};
};
chosen {
bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
};
soc: soc { };
firmware: firmware {
scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
};
android {
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait,slotselect,avb";
status = "ok"
};
};
};
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
slim_aud: slim@3ac0000 {
cell-index = <1>;
compatible = "qcom,slim-ngd";
reg = <0x3ac0000 0x2c000>,
<0x3a84000 0x22000>;
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
qcom,apps-ch-pipes = <0x0>;
qcom,ea-pc = <0x3d0>;
iommus = <&apps_smmu 0x2026 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok"
/* Slimbus Slave DT for QCA6490 */
btfmslim_codec: qca6490 {
compatible = "qcom,btfmslim_slave";
elemental-addr = [00 01 21 02 17 02];
qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
qcom,btfm-slim-ifd-elemental-addr = [00 00 21 02 17 02];
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17a00000 0x10000>, /* GICD */
<0x17a60000 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,shima-pdc";
reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
<55 306 4>, <59 312 3>, <62 374 2>,
<64 434 2>, <66 438 3>, <69 86 1>,
<70 520 54>, <124 609 31>, <155 63 1>,
<156 716 12>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
wdog: qcom,wdt@17c10000 {
compatible = "qcom,msm-watchdog";
reg = <0x17c10000 0x1000>;
reg-names = "wdt-base";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
memtimer: timer@17c20000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17c20000 0x1000>;
clock-frequency = <19200000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c27000 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
dcc: dcc_v2@117f000 {
compatible = "qcom,dcc-v2";
reg = <0x117f000 0x1000>,
<0x1112000 0x6000>;
qcom,transaction_timeout = <0>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x12000>;
};
jtag_mm0: jtagmm@7040000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7040000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm1: jtagmm@7140000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7140000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm2: jtagmm@7240000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7240000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm3: jtagmm@7340000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7340000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
jtag_mm4: jtagmm@7440000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7440000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU4>;
};
jtag_mm5: jtagmm@7540000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7540000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU5>;
};
jtag_mm6: jtagmm@7640000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7640000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU6>;
};
jtag_mm7: jtagmm@7740000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7740000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU7>;
};
kryo-erp {
compatible = "arm,arm64-kryo-cpu-erp";
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
};
pil_scm_pas {
compatible = "qcom,pil-tz-scm-pas";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
};
qcom,mpm2-sleep-counter@c221000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0xc221000 0x1000>;
clock-frequency = <32768>;
};
cpu_pmu: cpu-pmu {
compatible = "arm,armv8-pmuv3";
qcom,irq-is-percpu;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
qcom-secure-buffer {
compatible = "qcom,secure-buffer";
qcom,vmid-cp-camera-preview-ro;
};
qcom-mem-buf {
compatible = "qcom,mem-buf";
qcom,mem-buf-capabilities = "supplier";
};
qcom,memshare {
compatible = "qcom,memshare";
qcom,client_1 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x0>;
qcom,client-id = <0>;
qcom,allocate-boot-time;
label = "modem";
};
qcom,client_2 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x0>;
qcom,client-id = <2>;
label = "modem";
};
qcom,client_3 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x500000>;
memory-region = <&memshare_mem>;
qcom,client-id = <1>;
qcom,allocate-on-request;
label = "modem";
};
};
qcom,msm-imem@146aa000 {
compatible = "qcom,msm-imem";
reg = <0x146aa000 0x1000>;
ranges = <0x0 0x146aa000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 0xc8>;
};
pil@6dc {
compatible = "qcom,msm-imem-pil-disable-timeout";
reg = <0x6dc 0x4>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
hyp_core_ctl: qcom,hyp-core-ctl {
compatible = "qcom,hyp-core-ctl";
status = "ok"
};
eud: qcom,msm-eud@88e0000 {
compatible = "qcom,msm-eud";
interrupt-names = "eud_irq";
interrupt-parent = <&pdc>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x088e0000 0x2000>,
<0x088e2000 0x1000>;
reg-names = "eud_base", "eud_mode_mgr2";
qcom,secure-eud-en;
status = "ok"
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <38400000>;
clock-output-names = "xo_board";
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-output-names = "chip_sleep_clk";
#clock-cells = <0>;
};
pcie_0_pipe_clk: pcie-0-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
};
pcie_1_pipe_clk: pcie-1-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_1_pipe_clk";
#clock-cells = <0>;
};
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <0>;
};
};
aopcc: qcom,aopcc {
compatible = "qcom,aop-qmp-clk";
mboxes = <&qmp_aop 0>;
mbox-names = "qdss_clk";
#clock-cells = <1>;
qcom,clk-stop-bimc-log;
};
gcc: clock-controller@100000 {
compatible = "qcom,shima-gcc", "syscon";
reg = <0x100000 0x1f0000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
camcc: clock-controller@ad00000 {
compatible = "qcom,shima-camcc", "syscon";
reg = <0xad00000 0x10000>;
reg-names = "cc_base";
vdd_mx-supply = <&VDD_MXA_LEVEL>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "cfg_ahb";
#clock-cells = <1>;
#reset-cells = <1>;
};
dispcc: clock-controller@af00000 {
compatible = "qcom,shima-dispcc", "syscon";
reg = <0xaf00000 0x20000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>, <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "gcc_disp_gpll0_clk_src",
"sleep_clk", "cfg_ahb";
#clock-cells = <1>;
#reset-cells = <1>;
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,shima-gpucc", "syscon";
reg = <0x3d90000 0x9000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src", "cfg_ahb";
#clock-cells = <1>;
#reset-cells = <1>;
};
videocc: clock-controller@abf0000 {
compatible = "qcom,shima-videocc", "syscon";
reg = <0xabf0000 0x10000>;
reg-names = "cc_base";
vdd_mx-supply = <&VDD_MXA_LEVEL>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "cfg_ahb";
#clock-cells = <1>;
#reset-cells = <1>;
};
apsscc: syscon@182a0000 {
compatible = "syscon";
reg = <0x182a0000 0x1c>;
};
mccc: syscon@90ba000 {
compatible = "syscon";
reg = <0x90ba000 0x54>;
};
debugcc: debug-clock-controller@0 {
compatible = "qcom,shima-debugcc";
qcom,gcc = <&gcc>;
qcom,videocc = <&videocc>;
qcom,camcc = <&camcc>;
qcom,dispcc = <&dispcc>;
qcom,gpucc = <&gpucc>;
qcom,apsscc = <&apsscc>;
qcom,mccc = <&mccc>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo_clk_src";
#clock-cells = <1>;
};
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw-epss";
reg = <0x18591000 0x1000>, <0x18592000 0x1000>,
<0x18593000 0x1000>;
reg-names = "freq-domain0", "freq-domain1",
"freq-domain2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
qcom,lut-row-size = <4>;
qcom,skip-enable-check;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int";
#freq-domain-cells = <2>;
};
qcom,cpufreq-hw-debug@18591000 {
compatible = "qcom,cpufreq-hw-epss-debug";
reg = <0x18591000 0x800>;
reg-names = "domain-top";
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>,
<&cpufreq_hw 2>;
};
qcom_tzlog: tz-log@0x146aa720 {
compatible = "qcom,tz-log";
reg = <0x146aa720 0x3000>;
qcom,hyplog-enabled;
hyplog-address-offset = <0x410>;
hyplog-size-offset = <0x414>;
};
qcom_qseecom: qseecom@c1800000 {
compatible = "qcom,qseecom";
memory-region = <&qseecom_mem>;
qcom,hlos-num-ce-hw-instances = <1>;
qcom,hlos-ce-hw-instance = <0>;
qcom,qsee-ce-hw-instance = <0>;
qcom,disk-encrypt-pipe-pair = <2>;
qcom,support-fde;
qcom,no-clock-support;
qcom,fde-key-size;
qcom,appsbl-qseecom-support;
qcom,commonlib64-loaded-by-uefi;
qcom,qsee-reentrancy-support = <2>;
};
qcom_rng: qrng@10d3000 {
compatible = "qcom,msm-rng";
reg = <0x10d3000 0x1000>;
qcom,no-qrng-config;
interconnect-names = "data_path";
interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_HWKM>;
clock-names = "km_clk_src";
clocks = <&rpmhcc RPMH_HWKM_CLK>;
};
qcom_cedev: qcedev@1de0000 {
compatible = "qcom,qcedev";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x24000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
qcom,bam-pipe-pair = <3>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,bam-ee = <0>;
qcom,smmu-s1-enable;
qcom,no-clock-support;
interconnect-names = "data_path";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
iommus = <&apps_smmu 0x0526 0x0011>;
qcom,iommu-dma = "atomic";
qcom_cedev_ns_cb {
compatible = "qcom,qcedev,context-bank";
label = "ns_context";
iommus = <&apps_smmu 0x532 0>,
<&apps_smmu 0x538 0>,
<&apps_smmu 0x539 0>,
<&apps_smmu 0x53F 0>;
};
qcom_cedev_s_cb {
compatible = "qcom,qcedev,context-bank";
label = "secure_context";
iommus = <&apps_smmu 0x533 0>,
<&apps_smmu 0x53C 0>,
<&apps_smmu 0x53D 0>,
<&apps_smmu 0x53E 0>;
qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
qcom,secure-context-bank;
};
};
qcom_crypto: qcrypto@1de0000 {
compatible = "qcom,qcrypto";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x24000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
qcom,bam-pipe-pair = <2>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,bam-ee = <0>;
qcom,ce-hw-shared;
qcom,clk-mgmt-sus-res;
qcom,use-sw-aes-cbc-ecb-ctr-algo;
qcom,use-sw-aes-xts-algo;
qcom,use-sw-aes-ccm-algo;
qcom,use-sw-ahash-algo;
qcom,use-sw-aead-algo;
qcom,use-sw-hmac-algo;
qcom,smmu-s1-enable;
qcom,no-clock-support;
interconnect-names = "data_path";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
iommus = <&apps_smmu 0x0524 0x0011>;
qcom,iommu-dma = "atomic";
};
qtee_shmbridge {
compatible = "qcom,tee-shared-memory-bridge";
};
qcom_smcinvoke {
compatible = "qcom,smcinvoke";
};
ipcc_mproc: qcom,ipcc@408000 {
compatible = "qcom,ipcc";
reg = <0x408000 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
qcom,trustedvm@d0800000 {
compatible = "qcom,pil-tz-generic";
status = "ok"
qcom,pas-id = <28>;
qcom,firmware-name = "trustedvm";
memory-region = <&pil_trustedvm_mem>;
};
qcom,guestvm_loader {
compatible = "qcom,guestvm-loader";
image_to_be_loaded = "trustedvm";
};
qcom,svm_neuron_block {
compatible = "qcom,neuron-service";
#address-cells = <1>;
#size-cells = <0>;
protocol {
compatible = "qcom,neuron-protocol-block";
processes = "server";
};
application {
compatible = "qcom,neuron-block-server";
};
channel@0 {
compatible = "qcom,neuron-channel-haven-shmem";
reg = <0>;
class = "message-queue";
direction = "receive";
max-size = <0 65536>;
shared-buffer = <&chan0_shbuf>;
qcom,primary;
haven-label = <1>;
peer-name = <2>;
};
channel@1 {
compatible = "qcom,neuron-channel-haven-shmem";
reg = <1>;
class = "message-queue";
direction = "send";
max-size = <0 65536>;
shared-buffer = <&chan1_shbuf>;
qcom,primary;
haven-label = <2>;
peer-name = <2>;
};
};
qrtr-haven {
compatible = "qcom,qrtr-haven";
qcom,master;
haven-label = <3>;
peer-name = <2>;
shared-buffer = <&qrtr_shbuf>;
};
tcsr_mutex_block: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_block 0 0x1000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1fc0000 {
compatible = "syscon";
reg = <0x1fc0000 0x30000>;
};
smem: qcom,smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
qcom,smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
qcom,entry-name = "rdbg";
#qcom,smem-state-cells = <1>;
};
smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
qcom,entry-name = "rdbg";
interrupt-controller;
#interrupt-cells = <2>;
};
sleepstate_smp2p_out: sleepstate-out {
qcom,entry-name = "sleepstate";
#qcom,smem-state-cells = <1>;
};
sleepstate_smp2p_in: qcom,sleepstate-in {
qcom,entry-name = "sleepstate_see";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p_sleepstate {
compatible = "qcom,smp2p-sleepstate";
qcom,smem-states = <&sleepstate_smp2p_out 0>;
interrupt-parent = <&sleepstate_smp2p_in>;
interrupts = <0 0>;
interrupt-names = "smp2p-sleepstate-in";
};
qcom,smp2p-nsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
qcom,entry-name = "rdbg";
#qcom,smem-state-cells = <1>;
};
smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
qcom,entry-name = "rdbg";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
/* ipa - inbound entry from mss */
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,glink {
compatible = "qcom,glink";
#address-cells = <1>;
#size-cells = <1>;
ranges;
glink_modem: modem {
qcom,remote-pid = <1>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "mpss_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,glink-label = "mpss";
qcom,modem_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,modem_ds {
qcom,glink-channels = "DS";
qcom,intents = <0x4000 0x2>;
};
qcom,modem_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_adsp>;
};
};
glink_adsp: adsp {
qcom,remote-pid = <2>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "adsp_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "adsp";
qcom,glink-label = "lpass";
qcom,adsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,adsp_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_modem>,
<&glink_cdsp>;
};
qcom,pmic_glink_rpmsg {
qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
};
qcom,pmic_glink_log_rpmsg {
qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
qcom,intents = <0x800 5
0xc00 3>;
};
};
glink_cdsp: cdsp {
qcom,remote-pid = <5>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "dsps_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "cdsp";
qcom,glink-label = "cdsp";
qcom,cdsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,cdsp_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_adsp>;
};
qcom,msm_cdsprm_rpmsg {
compatible = "qcom,msm-cdsprm-rpmsg";
qcom,glink-channels = "cdsprmglink-apps-dsp";
qcom,intents = <0x20 12>;
msm_cdsp_rm: qcom,msm_cdsp_rm {
compatible = "qcom,msm-cdsp-rm";
qcom,qos-latency-us = <70>;
qcom,qos-maxhold-ms = <20>;
};
};
};
};
qcom,glinkpkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-at-mdm0 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DS";
qcom,glinkpkt-dev-name = "at_mdm0";
};
qcom,glinkpkt-apr-apps2 {
qcom,glinkpkt-edge = "adsp";
qcom,glinkpkt-ch-name = "apr_apps2";
qcom,glinkpkt-dev-name = "apr_apps2";
};
qcom,glinkpkt-data40-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA40_CNTL";
qcom,glinkpkt-dev-name = "smdcntl8";
};
qcom,glinkpkt-data1 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA1";
qcom,glinkpkt-dev-name = "smd7";
};
qcom,glinkpkt-data4 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA4";
qcom,glinkpkt-dev-name = "smd8";
};
qcom,glinkpkt-data11 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA11";
qcom,glinkpkt-dev-name = "smd11";
};
};
qcom,venus@aab0000 {
compatible = "qcom,pil-tz-generic";
reg = <0xaab0000 0x2000>;
vdd-supply = <&video_cc_mvs0c_gdsc>;
qcom,proxy-reg-names = "vdd";
qcom,complete-ramdump;
clocks = <&videocc VIDEO_CC_XO_CLK>,
<&videocc VIDEO_CC_MVS0C_CLK>,
<&videocc VIDEO_CC_AHB_CLK>;
clock-names = "xo", "core", "ahb";
qcom,proxy-clock-names = "xo", "core", "ahb";
qcom,core-freq = <200000000>;
qcom,ahb-freq = <200000000>;
qcom,pas-id = <9>;
interconnect-names = "pil-venus";
interconnects = <&mmss_noc MASTER_VIDEO_P0
&mc_virt SLAVE_EBI1>;
qcom,proxy-timeout-ms = <100>;
qcom,firmware-name = "venus";
memory-region = <&pil_video_mem>;
};
qmp_aop: qcom,qmp-aop@c300000 {
compatible = "qcom,qmp-mbox";
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "aop_qmp";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
reg = <0xc300000 0x400>;
reg-names = "msgram";
label = "aop";
qcom,early-boot;
priority = <0>;
mbox-desc-offset = <0x0>;
#mbox-cells = <1>;
};
aop-msg-client {
compatible = "qcom,debugfs-qmp-client";
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
};
qcom,evass@abb0000 {
compatible = "qcom,pil-tz-generic";
reg = <0xabb0000 0x2000>;
status = "ok"
qcom,pas-id = <26>;
qcom,firmware-name = "evass";
memory-region = <&pil_cvp_mem>;
};
qcom,rmtfs_sharedmem@0 {
compatible = "qcom,sharedmem-uio";
reg = <0x0 0x280000>;
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
qcom,vm-nav-path;
};
qcom_hwkm: hwkm@10c0000 {
compatible = "qcom,hwkm";
reg = <0x10c0000 0x9000>, <0x1d90000 0x9000>;
reg-names = "km_master", "ice_slave";
qcom,enable-hwkm-clk;
clock-names = "km_clk_src";
clocks = <&rpmhcc RPMH_HWKM_CLK>;
qcom,op-freq-hz = <75000000>;
};
ufsphy_mem: ufsphy_mem@1d87000 {
reg = <0x1d87000 0xe10>;
reg-names = "phy_mem";
#phy-cells = <0>;
lanes-per-direction = <2>;
clock-names = "ref_clk_src",
"ref_clk",
"ref_aux_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_1_CLKREF_EN>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
resets = <&ufshc_mem 0>;
status = "disabled";
};
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>,
<0x1d88000 0x8000>,
<0x1d90000 0x9000>;
reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
#reset-cells = <1>;
/* UFS gear4 cfgReady bypass WA */
bypass-g4-cfgready;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
interconnect-names = "ufs-ddr", "cpu-ufs";
qcom,ufs-bus-bw,name = "ufshc_mem";
qcom,ufs-bus-bw,num-cases = <26>;
qcom,ufs-bus-bw,num-paths = <2>;
qcom,ufs-bus-bw,vectors-KBps =
/*
* During HS G3 UFS runs at nominal voltage corner, vote
* higher bandwidth to push other buses in the data path
* to run at nominal to achieve max throughput.
* 4GBps pushes BIMC to run at nominal.
* 200MBps pushes CNOC to run at nominal.
* Vote for half of this bandwidth for HS G3 1-lane.
* For max bandwidth, vote high enough to push the buses
* to run in turbo voltage corner.
*/
<0 0>, <0 0>, /* No vote */
<922 0>, <1000 0>, /* PWM G1 */
<1844 0>, <1000 0>, /* PWM G2 */
<3688 0>, <1000 0>, /* PWM G3 */
<7376 0>, <1000 0>, /* PWM G4 */
<1844 0>, <1000 0>, /* PWM G1 L2 */
<3688 0>, <1000 0>, /* PWM G2 L2 */
<7376 0>, <1000 0>, /* PWM G3 L2 */
<14752 0>, <1000 0>, /* PWM G4 L2 */
<127796 0>, <1000 0>, /* HS G1 RA */
<255591 0>, <1000 0>, /* HS G2 RA */
<2097152 0>, <102400 0>, /* HS G3 RA */
<4194304 0>, <204800 0>, /* HS G4 RA */
<255591 0>, <1000 0>, /* HS G1 RA L2 */
<511181 0>, <1000 0>, /* HS G2 RA L2 */
<4194304 0>, <204800 0>, /* HS G3 RA L2 */
<8388608 0>, <409600 0>, /* HS G4 RA L2 */
<149422 0>, <1000 0>, /* HS G1 RB */
<298189 0>, <1000 0>, /* HS G2 RB */
<2097152 0>, <102400 0>, /* HS G3 RB */
<4194304 0>, <204800 0>, /* HS G4 RB */
<298189 0>, <1000 0>, /* HS G1 RB L2 */
<596378 0>, <1000 0>, /* HS G2 RB L2 */
/* As UFS working in HS G3 RB L2 mode, aggregated
* bandwidth (AB) should take care of providing
* optimum throughput requested. However, as tested,
* in order to scale up CNOC clock, instantaneous
* bindwidth (IB) needs to be given a proper value too.
*/
<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
<7643136 0>, <307200 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
"MAX";
reset-gpios = <&tlmm 204 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
iommus = <&apps_smmu 0x80 0x0>;
qcom,iommu-dma = "fastmap";
dma-coherent;
rpm-level = <3>;
/*
* Hynix UFS2.2 is drawing 40mA current during APPS PC.
* Issue is seen only if PX10 is turned off and Vccq2 is ON.
* Since Vccq2 is always-on supply we can't turn it off,
* so don't turn off PX10, by updating spm_lvl to 3.
* In sleep state (spm-lvl=3) its drawing only .5mA.
*/
spm-level = <3>;
status = "disabled";
qos0 {
mask = <0xf0>;
vote = <59>;
};
qos1 {
mask = <0x0f>;
vote = <65>;
};
};
sdhc_1: sdhci@7C4000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>,
<0x007c8000 0x8000>, <0x7d0000 0x9000>;
reg-names = "hc_mem", "cqhci_mem", "cqhci_ice",
"cqhci_ice_hwkm";
iommus = <&apps_smmu 0xc0 0x0>;
dma-coherent;
qcom,iommu-dma = "bypass";
interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "core", "iface", "ice_core";
qcom,ice-clk-rates = <300000000 100000000>;
interconnects = <&aggre1_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDC_1>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
qcom,msm-bus,name = "sdhc1";
qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
/* No Vote */
<0 0>, <0 0>,
/* 400 KB/s*/
<1000 590000>, <2000 1590000>,
/* 25 MB/s */
<50000 590000>, <30000 1590000>,
/* 50 MB/s */
<80000 590000>, <40000 1590000>,
/* 100 MB/s */
<100000 590000>, <50000 1590000>,
/* 200 MB/s */
<150000 2060000>, <80000 6440000>,
/* 400 MB/s */
<261438 2060000>, <300000 6440000>,
/* Max. bandwidth */
<1338562 4096000>, <1338562 9170000>;
qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
100000000 200000000 400000000 4294967295>;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x000f642c 0x0 0x1 0x2C010800 0x80040868>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
cap-mmc-hw-reset;
bus-width = <8>;
non-removable;
supports-cqe;
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
/* Add dt entry for gcc hw reset */
resets = <&gcc GCC_SDCC1_BCR>;
reset-names = "core_reset";
status = "disabled";
qos0 {
mask = <0x0f>;
vote = <61>;
};
qos1 {
mask = <0xf0>;
vote = <67>;
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
reg-names = "hc_mem";
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
bus-width = <4>;
iommus = <&apps_smmu 0x4a0 0x0>;
dma-coherent;
qcom,iommu-dma = "bypass";
interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
qcom,msm-bus,name = "sdhc2";
qcom,msm-bus,num-cases = <7>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
/* No Vote */
<0 0>, <0 0>,
/* 400 KB/s*/
<1000 590000>, <2000 1590000>,
/* 25 MB/s */
<50000 590000>, <30000 1590000>,
/* 50 MB/s */
<80000 590000>, <40000 1590000>,
/* 100 MB/s */
<100000 590000>, <50000 1590000>,
/* 200 MB/s */
<261438 2060000>, <300000 6440000>,
/* Max. bandwidth */
<1338562 4096000>, <1338562 9170000>;
qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
100000000 200000000 4294967295>;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
qcom,devfreq,freq-table = <50000000 202000000>;
status = "disabled";
qos0 {
mask = <0x0f>;
vote = <61>;
};
qos1 {
mask = <0xf0>;
vote = <67>;
};
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x18200000 0x10000>,
<0x18210000 0x10000>,
<0x18220000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 0>;
rpmhcc: qcom,rpmhclk {
compatible = "qcom,shima-rpmh-clk";
#clock-cells = <1>;
};
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
system_pm {
compatible = "qcom,system-pm";
};
};
disp_rsc: rsc@af20000 {
label = "disp_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0xaf20000 0x10000>;
reg-names = "drv-0";
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0x1c00>;
qcom,drv-id = <0>;
qcom,tcs-config = <ACTIVE_TCS 0>,
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
disp_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
};
sde_rsc_rpmh {
compatible = "qcom,sde-rsc-rpmh";
cell-index = <0>;
};
};
spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0x1100>,
<0xc600000 0x2000000>,
<0xe600000 0x100000>,
<0xe700000 0xa0000>,
<0xc40a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
qcom,channel = <0>;
qcom,ee = <0>;
};
spmi_debug_bus: qcom,spmi-debug@6b12000 {
compatible = "qcom,spmi-pmic-arb-debug";
reg = <0x6b12000 0x60>, <0x7820b0 0x4>;
reg-names = "core", "fuse";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,fuse-disable-bit = <24>;
#address-cells = <2>;
#size-cells = <0>;
status = "disabled";
qcom,pmk8350-debug@0 {
compatible = "qcom,spmi-pmic";
reg = <0 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8350-debug@1 {
compatible = "qcom,spmi-pmic";
reg = <1 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8350c-debug@2 {
compatible = "qcom,spmi-pmic";
reg = <2 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8350b-debug@3 {
compatible = "qcom,spmi-pmic";
reg = <3 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pmr735b-debug@5 {
compatible = "qcom,spmi-pmic";
reg = <5 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
};
qcom,pmic_glink {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
qcom,subsys-name = "adsp";
qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
battery_charger: qcom,battery_charger {
compatible = "qcom,battery-charger";
};
qcom,ucsi {
compatible = "qcom,ucsi-glink";
port {
usb_port0_connector: endpoint {
remote-endpoint = <&usb_port0>;
};
};
};
altmode: qcom,altmode {
compatible = "qcom,altmode-glink";
#altmode-cells = <1>;
};
};
qcom,pmic_glink_log {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
qcom,battery_debug {
compatible = "qcom,battery-debug";
};
spmi_glink_debug: qcom,spmi_glink_debug {
compatible = "qcom,spmi-glink-debug";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* Primary SPMI bus */
spmi@0 {
reg = <0>;
#address-cells = <2>;
#size-cells = <0>;
qcom,pm8350b-debug@3 {
compatible = "qcom,spmi-pmic";
reg = <3 SPMI_USID>;
qcom,can-sleep;
};
};
/* Secondary (QUP) SPMI bus */
spmi@1 {
reg = <1>;
#address-cells = <2>;
#size-cells = <0>;
qcom,smb1394-debug@b {
compatible = "qcom,spmi-pmic";
reg = <11 SPMI_USID>;
qcom,can-sleep;
};
qcom,smb1394-debug@c {
compatible = "qcom,spmi-pmic";
reg = <12 SPMI_USID>;
qcom,can-sleep;
};
};
};
};
qcom,chd {
compatible = "qcom,core-hang-detect";
label = "core";
qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058
0x18040058 0x18050058 0x18060058 0x18070058>;
qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060
0x18040060 0x18050060 0x18060060 0x18070060>;
};
dload_mode {
compatible = "qcom,dload-mode";
};
cache-controller@9200000 {
compatible = "qcom,shima-llcc", "qcom,llcc-v2";
reg = <0x9200000 0xd0000> , <0x9600000 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
cap-based-alloc-and-pwr-collapse;
clocks = <&aopcc QDSS_CLK>;
clock-names = "qdss_clk";
};
clk_virt: interconnect {
compatible = "qcom,shima-clk_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
config_noc: interconnect@1500000 {
reg = <0x1500000 0x14080>;
compatible = "qcom,shima-config_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@1580000 {
reg = <0x1580000 0x4>;
compatible = "qcom,shima-mc_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp";
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
};
system_noc: interconnect@1680000 {
reg = <0x1680000 0x13480>;
compatible = "qcom,shima-system_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,shima-aggre1_noc";
reg = <0x016e0000 0x1f080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
};
aggre2_noc: interconnect@1700000 {
reg = <0x1700000 0x2c080>;
compatible = "qcom,shima-aggre2_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&rpmhcc RPMH_IPA_CLK>;
};
mmss_noc: interconnect@1740000 {
reg = <0x1740000 0x1e100>;
compatible = "qcom,shima-mmss_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp";
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
};
lpass_ag_noc: interconnect@3c40000 {
reg = <0x03c40000 0xf080>;
compatible = "qcom,shima-lpass_ag_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
dc_noc: interconnect@90e0000 {
reg = <0x90e0000 0x5080>;
compatible = "qcom,shima-dc_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect@9100000 {
reg = <0x9100000 0xb4000>;
compatible = "qcom,shima-gem_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp";
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
};
nsp_noc: interconnect@a0c0000 {
reg = <0x0a0c0000 0x10000>;
compatible = "qcom,shima-nsp_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
epss_l3_cpu: l3_cpu@18590000 {
reg = <0x18590000 0x4000>;
compatible = "qcom,lahaina-epss-l3-cpu";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPLL0>;
};
llcc_pmu: llcc-pmu@9095000 {
compatible = "qcom,llcc-pmu-ver2";
reg = <0x09095000 0x300>;
reg-names = "lagg-base";
};
llcc_bw_opp_table: llcc-bw-opp-table {
compatible = "operating-points-v2";
BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
BW_OPP_ENTRY( 1066, 16); /* 15258 MB/s */
};
ddr_bw_opp_table: ddr-bw-opp-table {
compatible = "operating-points-v2";
BW_OPP_ENTRY_DDR( 200, 4, 0x180); /* 762 MB/s */
BW_OPP_ENTRY_DDR( 451, 4, 0x180); /* 1720 MB/s */
BW_OPP_ENTRY_DDR( 547, 4, 0x180); /* 2086 MB/s */
BW_OPP_ENTRY_DDR( 768, 4, 0x180); /* 2929 MB/s */
BW_OPP_ENTRY_DDR( 1017, 4, 0x180); /* 3879 MB/s */
BW_OPP_ENTRY_DDR( 1555, 4, 0x180); /* 5931 MB/s */
BW_OPP_ENTRY_DDR( 1708, 4, 0x180); /* 6515 MB/s */
BW_OPP_ENTRY_DDR( 2092, 4, 0x100); /* 7980 MB/s */
BW_OPP_ENTRY_DDR( 2133, 4, 0x80); /* 8136 MB/s */
BW_OPP_ENTRY_DDR( 2736, 4, 0x100); /* 10437 MB/s */
BW_OPP_ENTRY_DDR( 3196, 4, 0x100); /* 12191 MB/s */
};
qoslat_opp_table: qoslat-opp-table {
compatible = "operating-points-v2";
opp-1 {
opp-hz = /bits/ 64 < 1 >;
};
opp-2 {
opp-hz = /bits/ 64 < 2 >;
};
};
cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
compatible = "qcom,devfreq-icc";
governor = "bw_hwmon";
interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
compatible = "qcom,bimc-bwmon4";
reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&cpu_cpu_llcc_bw>;
qcom,count-unit = <0x10000>;
};
cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
compatible = "qcom,devfreq-icc-ddr";
governor = "bw_hwmon";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@9091000 {
compatible = "qcom,bimc-bwmon5";
reg = <0x9091000 0x1000>;
reg-names = "base";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&cpu_llcc_ddr_bw>;
qcom,count-unit = <0x10000>;
};
cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU0>;
};
cpu1_cpu_l3_lat: qcom,cpu1-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU1>;
};
cpu2_cpu_l3_lat: qcom,cpu2-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU2>;
};
cpu3_cpu_l3_lat: qcom,cpu3-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU3>;
};
cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU4>;
};
cpu5_cpu_l3_lat: qcom,cpu5-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU5>;
};
cpu6_cpu_l3_lat: qcom,cpu6-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU6>;
};
cpu7_cpu_l3_lat: qcom,cpu7-cpu-l3-lat {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "mem_latency";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_CPU7>;
};
cpu7_cpu_l3_latfloor: qcom,cpu7-cpu-l3-latfloor {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "compute";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_SHARED>;
};
cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
compatible = "qcom,devfreq-icc";
governor = "mem_latency";
interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {
compatible = "qcom,devfreq-icc";
governor = "mem_latency";
interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
compatible = "qcom,devfreq-icc-ddr";
governor = "mem_latency";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {
compatible = "qcom,devfreq-icc-ddr";
governor = "mem_latency";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc-ddr";
governor = "compute";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc-ddr";
governor = "compute";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu4_cpu_llcc_latfloor: qcom,cpu4-cpu-llcc-latfloor {
compatible = "qcom,devfreq-icc";
governor = "compute";
interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu7_cpu_ddr_latfloor: qcom,cpu7-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc-ddr";
governor = "compute";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu4_cpu_ddr_qoslat: qcom,cpu4-cpu-ddr-qoslat {
compatible = "qcom,devfreq-qoslat";
governor = "mem_latency";
operating-points-v2 = <&qoslat_opp_table>;
mboxes = <&qmp_aop 0>;
};
cpu0_cpu_l3_tbl: qcom,cpu0-cpu-l3-tbl {
qcom,core-dev-table =
< 300000 300000000 >,
< 691200 556800000 >,
< 940800 652800000 >,
< 1171200 844800000 >,
< 1516800 1056000000 >,
< 1670400 1305600000 >,
< 1804800 1420800000 >;
};
cpu4_cpu_l3_tbl: qcom,cpu4-cpu-l3-tbl {
qcom,core-dev-table =
< 940800 556800000 >,
< 1209600 806400000 >,
< 1651200 1190400000 >,
< 1900800 1401600000 >,
< 2361600 1420800000 >;
};
cpu7_cpu_l3_tbl: qcom,cpu7-cpu-l3-tbl {
qcom,core-dev-table =
< 1094400 556800000 >,
< 1267200 806400000 >,
< 1766400 1190400000 >,
< 2169600 1401600000 >,
< 2707200 1420800000 >;
};
cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
compatible = "qcom,arm-memlat-cpugrp";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0>;
qcom,target-dev = <&cpu0_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu1_cpu_l3_latmon: qcom,cpu1-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU1>;
qcom,target-dev = <&cpu1_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu2_cpu_l3_latmon: qcom,cpu2-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU2>;
qcom,target-dev = <&cpu2_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu3_cpu_l3_latmon: qcom,cpu3-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU3>;
qcom,target-dev = <&cpu3_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,core-dev-table = <&cpu0_cpu_l3_tbl>;
};
cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4>;
qcom,target-dev = <&cpu4_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,access-ev = <0x2B>;
qcom,wb-ev = <0x18>;
qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
};
cpu5_cpu_l3_latmon: qcom,cpu5-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU5>;
qcom,target-dev = <&cpu5_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,access-ev = <0x2B>;
qcom,wb-ev = <0x18>;
qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
};
cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU6>;
qcom,target-dev = <&cpu6_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,access-ev = <0x2B>;
qcom,wb-ev = <0x18>;
qcom,core-dev-table = <&cpu4_cpu_l3_tbl>;
};
cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu7_cpu_l3_lat>;
qcom,cachemiss-ev = <0x17>;
qcom,access-ev = <0x2B>;
qcom,wb-ev = <0x18>;
qcom,core-dev-table = <&cpu7_cpu_l3_tbl>;
};
cpu7_l3_computemon: qcom,cpu7-l3-computemon {
compatible = "qcom,arm-compute-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu7_cpu_l3_latfloor>;
qcom,core-dev-table =
< 2169600 300000000 >,
< 2707200 1420800000 >;
};
cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,target-dev = <&cpu0_cpu_llcc_lat>;
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,cachemiss-ev = <0x2A>;
qcom,core-dev-table =
< 1171200 MHZ_TO_MBPS( 300, 16) >,
< 1516800 MHZ_TO_MBPS( 466, 16) >,
< 1804800 MHZ_TO_MBPS( 600, 16) >;
};
cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,target-dev = <&cpu0_llcc_ddr_lat>;
qcom,cachemiss-ev = <0x1000>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 940800 MHZ_TO_MBPS( 451, 4) >,
< 1171200 MHZ_TO_MBPS( 547, 4) >,
< 1516800 MHZ_TO_MBPS( 768, 4) >,
< 1804800 MHZ_TO_MBPS( 1017, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 940800 MHZ_TO_MBPS( 451, 4) >,
< 1171200 MHZ_TO_MBPS( 547, 4) >,
< 1516800 MHZ_TO_MBPS( 768, 4) >,
< 1804800 MHZ_TO_MBPS( 1555, 4) >;
};
};
cpu0_computemon: qcom,cpu0-computemon {
compatible = "qcom,arm-compute-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
qcom,core-dev-table =
< 691000 MHZ_TO_MBPS( 200, 4) >,
< 1171200 MHZ_TO_MBPS( 451, 4) >,
< 1516800 MHZ_TO_MBPS( 547, 4) >,
< 1804800 MHZ_TO_MBPS( 768, 4) >;
};
cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,target-dev = <&cpu4_cpu_llcc_lat>;
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cachemiss-ev = <0x2A>;
qcom,core-dev-table =
< 691000 MHZ_TO_MBPS( 300, 16) >,
< 940800 MHZ_TO_MBPS( 466, 16) >,
< 1209600 MHZ_TO_MBPS( 600, 16) >,
< 1651800 MHZ_TO_MBPS( 806, 16) >,
< 2361600 MHZ_TO_MBPS( 933, 16) >,
< 2707200 MHZ_TO_MBPS( 1066, 16) >;
};
cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&cpu4_llcc_ddr_lat>;
qcom,cachemiss-ev = <0x1000>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 691000 MHZ_TO_MBPS( 451, 4) >,
< 940800 MHZ_TO_MBPS( 547, 4) >,
< 1209600 MHZ_TO_MBPS(1017, 4) >,
< 1651800 MHZ_TO_MBPS(1555, 4) >,
< 2361600 MHZ_TO_MBPS(1708, 4) >,
< 2707200 MHZ_TO_MBPS(2133, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 691000 MHZ_TO_MBPS( 451, 4) >,
< 940800 MHZ_TO_MBPS( 547, 4) >,
< 1209600 MHZ_TO_MBPS(1017, 4) >,
< 1651800 MHZ_TO_MBPS(1555, 4) >,
< 1900800 MHZ_TO_MBPS(1708, 4) >,
< 2361600 MHZ_TO_MBPS(2092, 4) >,
< 2707200 MHZ_TO_MBPS(3196, 4) >;
};
};
cpu4_computemon: qcom,cpu4-computemon {
compatible = "qcom,arm-compute-mon";
qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 691000 MHZ_TO_MBPS( 451, 4) >,
< 1209600 MHZ_TO_MBPS( 547, 4) >,
< 1497600 MHZ_TO_MBPS( 768, 4) >,
< 1651800 MHZ_TO_MBPS(1017, 4) >,
< 1900800 MHZ_TO_MBPS(1555, 4) >,
< 2361600 MHZ_TO_MBPS(1708, 4) >,
< 2707200 MHZ_TO_MBPS(2133, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 691000 MHZ_TO_MBPS( 451, 4) >,
< 1209600 MHZ_TO_MBPS( 547, 4) >,
< 1497600 MHZ_TO_MBPS( 768, 4) >,
< 1651800 MHZ_TO_MBPS(1017, 4) >,
< 1900800 MHZ_TO_MBPS(1708, 4) >,
< 2361600 MHZ_TO_MBPS(2092, 4) >,
< 2707200 MHZ_TO_MBPS(3196, 4) >;
};
};
cpu4_llcc_computemon: qcom,cpu4-llcc-computemon {
compatible = "qcom,arm-compute-mon";
qcom,target-dev = <&cpu4_cpu_llcc_latfloor>;
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,core-dev-table =
< 1900800 MHZ_TO_MBPS( 150, 16) >,
< 2707200 MHZ_TO_MBPS( 600, 16) >;
};
cpu7_computemon: qcom,cpu7-computemon {
compatible = "qcom,arm-compute-mon";
qcom,target-dev = <&cpu7_cpu_ddr_latfloor>;
qcom,cpulist = <&CPU7>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 2361600 MHZ_TO_MBPS( 451, 4) >,
< 2707200 MHZ_TO_MBPS(2133, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 2361600 MHZ_TO_MBPS( 451, 4) >,
< 2707200 MHZ_TO_MBPS(3196, 4) >;
};
};
cpu4_qoslatmon: qcom,cpu4-qoslatmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&cpu4_cpu_ddr_qoslat>;
qcom,cachemiss-ev = <0x1000>;
qcom,core-dev-table =
< 300000 1 >,
< 3000000 2 >;
};
};
qcom,sps {
compatible = "qcom,msm-sps-4k";
qcom,pipe-attr-ee;
};
pil_modem: qcom,mss@4080000 {
compatible = "qcom,pil-tz-generic";
reg = <0x4080000 0x100>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
vdd_mss-supply = <&VDD_MODEM_LEVEL>;
qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
qcom,proxy-reg-names = "vdd_cx", "vdd_mss";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <4>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <421>;
qcom,sysmon-id = <0>;
qcom,minidump-id = <3>;
qcom,aux-minidump-ids = <4>;
qcom,ssctl-instance-id = <0x12>;
qcom,firmware-name = "modem";
memory-region = <&pil_mpss_wlan_mem>;
qcom,signal-aop;
qcom,complete-ramdump;
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
/* Inputs from mss */
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<&modem_smp2p_in 0 0>,
<&modem_smp2p_in 2 0>,
<&modem_smp2p_in 1 0>,
<&modem_smp2p_in 3 0>,
<&modem_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack",
"qcom,shutdown-ack";
/* Outputs to mss */
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
mboxes = <&qmp_aop 0>;
mbox-names = "mss-pil";
};
qcom,lpass@3700000 {
compatible = "qcom,pil-tz-generic";
reg = <0x3700000 0x00100>;
vdd_cx-supply = <&VDD_LPI_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
vdd_mx-supply = <&VDD_LPI_MX_LEVEL>;
qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
qcom,proxy-reg-names = "vdd_cx","vdd_mx";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <1>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <423>;
qcom,minidump-id = <5>;
qcom,sysmon-id = <1>;
qcom,ssctl-instance-id = <0x14>;
qcom,firmware-name = "adsp";
memory-region = <&pil_adsp_mem>;
qcom,signal-aop;
qcom,complete-ramdump;
qcom,minidump-as-elf32;
/* Inputs from lpass */
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&adsp_smp2p_in 0 0>,
<&adsp_smp2p_in 2 0>,
<&adsp_smp2p_in 1 0>,
<&adsp_smp2p_in 3 0>,
<&adsp_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack",
"qcom,shutdown-ack";
/* Outputs to lpass */
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
mboxes = <&qmp_aop 0>;
mbox-names = "adsp-pil";
};
qcom,turing@a300000 {
compatible = "qcom,pil-tz-generic";
reg = <0xa300000 0x100000>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
vdd_mx-supply = <&VDD_MXC_LEVEL>;
qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
qcom,proxy-reg-names = "vdd_cx","vdd_mx";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <18>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <601>;
qcom,minidump-id = <7>;
qcom,sysmon-id = <7>;
qcom,ssctl-instance-id = <0x17>;
qcom,firmware-name = "cdsp";
memory-region = <&pil_cdsp_mem>;
qcom,signal-aop;
qcom,complete-ramdump;
qcom,minidump-as-elf32;
interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
/* Inputs from turing */
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
<&cdsp_smp2p_in 0 0>,
<&cdsp_smp2p_in 2 0>,
<&cdsp_smp2p_in 1 0>,
<&cdsp_smp2p_in 3 0>,
<&cdsp_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack",
"qcom,shutdown-ack";
/* Outputs to turing */
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
mboxes = <&qmp_aop 0>;
mbox-names = "cdsp-pil";
};
qcom,msm-cdsp-loader {
compatible = "qcom,cdsp-loader";
qcom,proc-img-to-load = "cdsp";
};
qcom,msm-adsprpc-mem {
compatible = "qcom,msm-adsprpc-mem-region";
memory-region = <&adsp_mem>;
restrict-access;
};
thermal_zones: thermal-zones {
};
qmi_tmd: qmi-tmd-devices {
compatible = "qcom,qmi-cooling-devices";
};
tsens0:tsens@c222000 {
compatible = "qcom,tsens24xx";
reg = <0x0C222000 0x8>,
<0x0C263000 0x1ff>;
reg-names = "tsens_srot_physical",
"tsens_tm_physical";
interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 20 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tsens-upper-lower", "tsens-critical",
"tsens-0C";
tsens-reinit-wa;
#thermal-sensor-cells = <1>;
};
tsens1:tsens@c223000 {
compatible = "qcom,tsens24xx";
reg = <0x0C223000 0x8>,
<0x0C265000 0x1ff>;
reg-names = "tsens_srot_physical",
"tsens_tm_physical";
interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 21 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tsens-upper-lower", "tsens-critical",
"tsens-0C";
tsens-reinit-wa;
#thermal-sensor-cells = <1>;
};
msm_fastrpc: qcom,msm_fastrpc {
compatible = "qcom,msm-fastrpc-compute";
qcom,adsp-remoteheap-vmid = <22 37>;
qcom,fastrpc-adsp-audio-pdr;
qcom,fastrpc-adsp-sensors-pdr;
qcom,rpc-latency-us = <235>;
qcom,fastrpc-gids = <2908>;
qcom,qos-cores = <0 1 2 3>;
qcom,msm_fastrpc_compute_cb1 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2961 0x0400>,
<&apps_smmu 0x1981 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb2 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2962 0x0400>,
<&apps_smmu 0x1982 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb3 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2963 0x0400>,
<&apps_smmu 0x1983 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb4 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2964 0x0400>,
<&apps_smmu 0x1984 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb5 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2965 0x0400>,
<&apps_smmu 0x1985 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb6 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x02966 0x0400>,
<&apps_smmu 0x1986 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb7 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2967 0x0400>,
<&apps_smmu 0x1987 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb8 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x2968 0x0400>,
<&apps_smmu 0x1988 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb9 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
qcom,secure-context-bank;
iommus = <&apps_smmu 0x2969 0x0400>,
<&apps_smmu 0x1989 0x0420>;
qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb10 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&apps_smmu 0x2003 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb11 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&apps_smmu 0x2004 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb12 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&apps_smmu 0x2005 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
shared-cb = <5>;
};
qcom,msm_fastrpc_compute_cb13 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x198B 0x0420>,
<&apps_smmu 0x296B 0x0400>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb14 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x198C 0x0420>,
<&apps_smmu 0x296C 0x0400>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb15 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x198D 0x0420>,
<&apps_smmu 0x296D 0x0400>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb16 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x198E 0x0420>,
<&apps_smmu 0x296E 0x0400>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable", "HUPCF";
dma-coherent-hint-cached;
};
};
mem_dump {
compatible = "qcom,mem-dump";
memory-region = <&dump_mem>;
c0_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x0>;
};
c100_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x1>;
};
c200_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x2>;
};
c300_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x3>;
};
c400_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x4>;
};
c500_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x5>;
};
c600_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x6>;
};
c700_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x7>;
};
c0_scandump {
qcom,dump-size = <0x10100>;
qcom,dump-id = <0x130>;
};
c100_scandump {
qcom,dump-size = <0x10100>;
qcom,dump-id = <0x131>;
};
c200_scandump {
qcom,dump-size = <0x10100>;
qcom,dump-id = <0x132>;
};
c300_scandump {
qcom,dump-size = <0x10100>;
qcom,dump-id = <0x133>;
};
c400_scandump {
qcom,dump-size = <0x40000>;
qcom,dump-id = <0x134>;
};
c500_scandump {
qcom,dump-size = <0x40000>;
qcom,dump-id = <0x135>;
};
c600_scandump {
qcom,dump-size = <0x40000>;
qcom,dump-id = <0x136>;
};
c700_scandump {
qcom,dump-size = <0x40000>;
qcom,dump-id = <0x137>;
};
cpuss_reg {
qcom,dump-size = <0x30000>;
qcom,dump-id = <0xef>;
};
l1_icache0 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x60>;
};
l1_icache100 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x61>;
};
l1_icache200 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x62>;
};
l1_icache300 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x63>;
};
l1_icache400 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x64>;
};
l1_icache500 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x65>;
};
l1_icache600 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x66>;
};
l1_icache700 {
qcom,dump-size = <0x32100>;
qcom,dump-id = <0x67>;
};
l1_dcache0 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x80>;
};
l1_dcache100 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x81>;
};
l1_dcache200 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x82>;
};
l1_dcache300 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x83>;
};
l1_dcache400 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x84>;
};
l1_dcache500 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x85>;
};
l1_dcache600 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x86>;
};
l1_dcache700 {
qcom,dump-size = <0x12100>;
qcom,dump-id = <0x87>;
};
l1_itlb400 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x24>;
};
l1_itlb500 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x25>;
};
l1_itlb600 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x26>;
};
l1_itlb700 {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x27>;
};
l1_dtlb400 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x44>;
};
l1_dtlb500 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x45>;
};
l1_dtlb600 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x46>;
};
l1_dtlb700 {
qcom,dump-size = <0x3a0>;
qcom,dump-id = <0x47>;
};
l2_cache400 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc4>;
};
l2_cache500 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc5>;
};
l2_cache600 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc6>;
};
l2_cache700 {
qcom,dump-size = <0x120100>;
qcom,dump-id = <0xc7>;
};
l2_tlb0 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x120>;
};
l2_tlb100 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x121>;
};
l2_tlb200 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x122>;
};
l2_tlb300 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x123>;
};
l2_tlb400 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x124>;
};
l2_tlb500 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x125>;
};
l2_tlb600 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x126>;
};
l2_tlb700 {
qcom,dump-size = <0xc100>;
qcom,dump-id = <0x127>;
};
gemnoc {
qcom,dump-size = <0x100000>;
qcom,dump-id = <0x162>;
};
mhm_scan {
qcom,dump-size = <0x20000>;
qcom,dump-id = <0x161>;
};
rpmh {
qcom,dump-size = <0x2000000>;
qcom,dump-id = <0xec>;
};
rpm_sw {
qcom,dump-size = <0x28000>;
qcom,dump-id = <0xea>;
};
pmic {
qcom,dump-size = <0x200000>;
qcom,dump-id = <0xe4>;
};
fcm {
qcom,dump-size = <0x8400>;
qcom,dump-id = <0xee>;
};
etf_swao {
qcom,dump-size = <0x10000>;
qcom,dump-id = <0xf1>;
};
etr_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x100>;
};
etfswao_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x102>;
};
LLCC_1: llcc_1_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x140>;
};
LLCC_2: llcc_2_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x141>;
};
misc_data {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0xe8>;
};
etf_lpass {
qcom,dump-size = <0x4000>;
qcom,dump-id = <0xf4>;
};
etflpass_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x104>;
};
osm_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x163>;
};
pcu_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x164>;
};
fsm_data {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x165>;
};
};
qfprom: qfprom@780000 {
compatible = "qcom,qfprom";
reg = <0x780000 0x7000>;
#address-cells = <1>;
#size-cells = <1>;
read-only;
ranges;
gpu_speed_bin: gpu_speed_bin@1e1 {
reg = <0x1e1 0x2>;
bits = <5 8>;
};
gpu_gaming_bin: gpu_gaming_bin@1ed {
reg = <0x1ed 0x1>;
bits = <5 1>;
};
adsp_variant: adsp_variant@6020 {
reg = <0x6022 0x1>;
bits = <2 4>;
};
feat_conf_m7: feat_conf_m7@6020 {
reg = <0x6020 0x4>;
};
feat_conf_qc_spare_20_lsb: feat_conf_qc_spare_20_lsb@4700 {
reg = <0x4700 0x4>;
};
};
qfprom_sys: qfprom@0 {
compatible = "qcom,qfprom-sys";
nvmem-cells = <&gpu_speed_bin>,
<&gpu_gaming_bin>,
<&adsp_variant>,
<&feat_conf_m7>,
<&feat_conf_qc_spare_20_lsb>;
nvmem-cell-names = "gpu_speed_bin",
"gpu_gaming_bin",
"adsp_variant",
"feat_conf_m7",
"feat_conf_qc_spare_20_lsb";
};
wlan: qcom,cnss-qca6490@b0000000 {
compatible = "qcom,cnss-qca6490";
reg = <0xb0000000 0x10000>,
<0xb2e5510 0x690>;
reg-names = "smmu_iova_ipa", "tcs_cmd";
wlan-en-gpio = <&tlmm 64 0>;
qcom,bt-en-gpio = <&tlmm 65 0>;
pinctrl-names = "wlan_en_active", "wlan_en_sleep";
pinctrl-0 = <&cnss_wlan_en_active>;
pinctrl-1 = <&cnss_wlan_en_sleep>;
qcom,wlan-rc-num = <0>;
qcom,wlan-ramdump-dynamic = <0x420000>;
qcom,wlan-cbc-enabled;
/* RPMH_PDC_WLAN_RF_TCS<6>_CMD<0> offset */
qcom,tcs_offset_int_pow_amp_vreg = <0x4B0>;
cnss-enable-self-recovery;
vdd-wlan-aon-supply = <&S2C>;
qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>;
vdd-wlan-dig-supply = <&S2C>;
qcom,vdd-wlan-dig-config = <950000 952000 0 0 1>;
vdd-wlan-io-supply = <&S10B>;
qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
vdd-wlan-rfa1-supply = <&S11B>;
qcom,vdd-wlan-rfa1-config = <1880000 1880000 0 0 1>;
vdd-wlan-rfa2-supply = <&S12B>;
qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>;
wlan-ant-switch-supply = <&L11C>;
qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>;
interconnects =
<&aggre1_noc MASTER_PCIE_0 &aggre1_noc SLAVE_ANOC_PCIE_GEM_NOC>,
<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
qcom,icc-path-count = <2>;
qcom,bus-bw-cfg-count = <7>;
qcom,bus-bw-cfg =
/** ICC Path 1 **/
<0 0>, /* no vote */
/* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
<2250 390000>,
/* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
<7500 390000>,
/* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
<30000 790000>,
/* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */
<100000 790000>,
/* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */
<175000 1600000>,
/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz
* ddr: 547.2 MHz
*/
<7500 390000>,
/** ICC Path 2 **/
<0 0>,
<2250 1804800>,
<7500 1804800>,
<30000 1804800>,
<100000 1804800>,
<175000 6220800>,
<7500 2188800>;
mhi,max-channels = <30>;
mhi,timeout = <10000>;
mhi,buffer-len = <0x8000>;
mhi,m2-no-db-access;
mhi_channels {
#address-cells = <1>;
#size-cells = <0>;
mhi_chan@0 {
reg = <0>;
label = "LOOPBACK";
mhi,num-elements = <32>;
mhi,event-ring = <1>;
mhi,chan-dir = <1>;
mhi,data-type = <0>;
mhi,doorbell-mode = <2>;
mhi,ee = <0x14>;
};
mhi_chan@1 {
reg = <1>;
label = "LOOPBACK";
mhi,num-elements = <32>;
mhi,event-ring = <1>;
mhi,chan-dir = <2>;
mhi,data-type = <0>;
mhi,doorbell-mode = <2>;
mhi,ee = <0x14>;
};
mhi_chan@4 {
reg = <4>;
label = "DIAG";
mhi,num-elements = <32>;
mhi,event-ring = <1>;
mhi,chan-dir = <1>;
mhi,data-type = <0>;
mhi,doorbell-mode = <2>;
mhi,ee = <0x14>;
};
mhi_chan@5 {
reg = <5>;
label = "DIAG";
mhi,num-elements = <32>;
mhi,event-ring = <1>;
mhi,chan-dir = <2>;
mhi,data-type = <0>;
mhi,doorbell-mode = <2>;
mhi,ee = <0x14>;
};
mhi_chan@20 {
reg = <20>;
label = "IPCR";
mhi,num-elements = <32>;
mhi,event-ring = <1>;
mhi,chan-dir = <1>;
mhi,data-type = <1>;
mhi,doorbell-mode = <2>;
mhi,ee = <0x14>;
mhi,auto-start;
};
mhi_chan@21 {
reg = <21>;
label = "IPCR";
mhi,num-elements = <32>;
mhi,event-ring = <1>;
mhi,chan-dir = <2>;
mhi,data-type = <0>;
mhi,doorbell-mode = <2>;
mhi,ee = <0x14>;
mhi,auto-queue;
mhi,auto-start;
};
};
mhi_events {
mhi_event@0 {
mhi,num-elements = <32>;
mhi,intmod = <0>;
mhi,msi = <1>;
mhi,priority = <1>;
mhi,brstmode = <2>;
mhi,data-type = <1>;
};
mhi_event@1 {
mhi,num-elements = <256>;
mhi,intmod = <0>;
mhi,msi = <2>;
mhi,priority = <1>;
mhi,brstmode = <2>;
};
mhi_event@2 {
mhi,num-elements = <32>;
mhi,intmod = <0>;
mhi,msi = <0>;
mhi,priority = <2>;
mhi,brstmode = <2>;
mhi,data-type = <3>;
};
};
mhi_devices {
mhi_qrtr {
mhi,chan = "IPCR";
qcom,net-id = <0>;
qcom,low-latency;
};
};
};
bluetooth: bt_qca6490 {
compatible = "qcom,qca6490";
pinctrl-names = "default";
pinctrl-0 = <&bt_en_sleep>;
qcom,bt-reset-gpio = <&tlmm 65 0>; /* BT_EN */
qcom,bt-sw-ctrl-gpio = <&tlmm 91 0>; /* SW_CTRL */
qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */
qcom,bt-vdd-io-supply = <&S10B>;
qcom,bt-vdd-aon-supply = <&S2C>;
qcom,bt-vdd-dig-supply = <&S2C>;
qcom,bt-vdd-rfacmn-supply = <&S2C>;
qcom,bt-vdd-rfa-0p8-supply = <&S2C>;
qcom,bt-vdd-rfa1-supply = <&S11B>;
qcom,bt-vdd-rfa2-supply = <&S12B>;
qcom,bt-vdd-asd-supply = <&L11C>;
qcom,bt-vdd-io-config = <1800000 1800000 0 1>;
qcom,bt-vdd-aon-config = <950000 952000 0 1>;
qcom,bt-vdd-dig-config = <950000 952000 0 1>;
qcom,bt-vdd-rfacmn-config = <950000 952000 0 1>;
qcom,bt-vdd-rfa-0p8-config = <950000 952000 0 1>;
qcom,bt-vdd-rfa1-config = <1880000 1880000 0 1>;
qcom,bt-vdd-rfa2-config = <1350000 1350000 0 1>;
qcom,bt-vdd-asd-config = <2800000 2800000 0 1>;
};
qcom,msm_gsi {
compatible = "qcom,msm_gsi";
};
qcom,rmnet-ipa {
compatible = "qcom,rmnet-ipa3";
qcom,rmnet-ipa-ssr;
qcom,ipa-platform-type-msm;
qcom,ipa-advertise-sg-support;
qcom,ipa-napi-enable;
};
qcom,ipa_fws {
compatible = "qcom,pil-tz-generic";
qcom,pas-id = <0xf>;
qcom,firmware-name = "ipa_fws";
qcom,pil-force-shutdown;
memory-region = <&pil_ipa_gsi_mem>;
};
ipa_hw: qcom,ipa@1e00000 {
compatible = "qcom,ipa";
mboxes = <&qmp_aop 0>;
reg =
<0x1e00000 0x84000>,
<0x1e04000 0x23000>;
reg-names = "ipa-base", "gsi-base";
interrupts =
<0 654 IRQ_TYPE_LEVEL_HIGH>,
<0 432 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ipa-irq", "gsi-irq";
qcom,ipa-hw-ver = <19>; /* IPA core version = IPAv4.9 */
qcom,ipa-hw-mode = <0>;
qcom,platform-type = <1>; /* MSM platform */
qcom,ee = <0>;
qcom,use-ipa-tethering-bridge;
qcom,modem-cfg-emb-pipe-flt;
qcom,ipa-wdi3-over-gsi;
qcom,arm-smmu;
qcom,smmu-fast-map;
qcom,use-64-bit-dma-mask;
qcom,ipa-endp-delay-wa;
qcom,lan-rx-napi;
qcom,tx-napi;
qcom,wan-use-skb-page;
qcom,rmnet-ctl-enable;
qcom,ipa-uc-holb-monitor;
qcom,gsi_wdi_db_polling;
qcom,ipa-holb-monitor-poll-period = <5>;
qcom,ipa-holb-monitor-max-cnt-wlan = <10>;
qcom,ipa-holb-monitor-max-cnt-usb = <10>;
qcom,ipa-holb-monitor-max-cnt-11ad = <10>;
qcom,tx-wrapper-cache-max-size = <400>;
qcom,ipa-gpi-event-rp-ddr;
clock-names = "core_clk";
clocks = <&rpmhcc RPMH_IPA_CLK>;
qcom,interconnect,num-cases = <5>;
qcom,interconnect,num-paths = <3>;
interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
/* No vote */
qcom,no-vote =
<0 0 0 0 0 0>;
/* SVS2 */
qcom,svs2 =
<150000 600000 150000 1804000 0 74000>;
/* SVS */
qcom,svs =
<625000 1200000 625000 3072000 0 150000>;
/* NOMINAL */
qcom,nominal =
<1250000 2400000 1250000 6220800 0 400000>;
/* TURBO */
qcom,turbo =
<2000000 3500000 2000000 7219200 0 400000>;
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
"TURBO";
qcom,throughput-threshold = <600 2500 5000>;
qcom,scaling-exceptions = <>;
/* smp2p information */
qcom,smp2p_map_ipa_1_out {
compatible = "qcom,smp2p-map-ipa-1-out";
qcom,smem-states = <&smp2p_ipa_1_out 0>;
qcom,smem-state-names = "ipa-smp2p-out";
};
qcom,smp2p_map_ipa_1_in {
compatible = "qcom,smp2p-map-ipa-1-in";
interrupts-extended = <&smp2p_ipa_1_in 0 0>;
interrupt-names = "ipa-smp2p-in";
};
ipa_smmu_ap: ipa_smmu_ap {
compatible = "qcom,ipa-smmu-ap-cb";
iommus = <&apps_smmu 0x480 0x0>;
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
qcom,additional-mapping =
/* modem tables in IMEM */
<0x146A8000 0x146A8000 0x2000>;
dma-coherent;
qcom,iommu-dma = "fastmap";
qcom,ipa-q6-smem-size = <36864>;
};
ipa_smmu_wlan: ipa_smmu_wlan {
compatible = "qcom,ipa-smmu-wlan-cb";
iommus = <&apps_smmu 0x481 0x0>;
qcom,iommu-dma = "atomic";
dma-coherent;
};
ipa_smmu_uc: ipa_smmu_uc {
compatible = "qcom,ipa-smmu-uc-cb";
iommus = <&apps_smmu 0x482 0x0>;
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
qcom,iommu-dma = "atomic";
};
ipa_smmu_11ad: ipa_smmu_11ad {
compatible = "qcom,ipa-smmu-11ad-cb";
iommus = <&apps_smmu 0x483 0x0>;
dma-coherent;
qcom,shared-cb;
qcom,iommu-group = <>;
};
};
};
#include "shima-pinctrl.dtsi"
#include "shima-pm.dtsi"
#include "shima-regulators.dtsi"
#include "shima-qupv3.dtsi"
#include "shima-gdsc.dtsi"
#include "shima-ion.dtsi"
#include "shima-usb.dtsi"
#include "shima-pcie.dtsi"
#include "shima-coresight.dtsi"
#include "ipcc-test-shima.dtsi"
#include "msm-arm-smmu-shima.dtsi"
#include "shima-vidc.dtsi"
#include "shima-cvp.dtsi"
#include "shima-gpu.dtsi"
#include "display/shima-sde.dtsi"
#include "shima-audio.dtsi"
#include "shima-thermal.dtsi"
&pcie0_rp {
#address-cells = <5>;
#size-cells = <0>;
cnss_pci: cnss_pci {
reg = <0 0 0 0 0>;
qcom,iommu-group = <&cnss_pci_iommu_group>;
memory-region = <&cnss_wlan_mem>;
#address-cells = <1>;
#size-cells = <1>;
cnss_pci_iommu_group: cnss_pci_iommu_group {
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
"non-fatal";
};
};
};
&gcc_pcie_0_gdsc {
qcom,retain-regs;
status = "ok"
};
&gcc_pcie_1_gdsc {
qcom,retain-regs;
status = "ok"
};
&gcc_ufs_phy_gdsc {
qcom,retain-regs;
status = "ok"
};
&gcc_usb30_prim_gdsc {
qcom,retain-regs;
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc {
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_mdp0_gdsc {
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_mdp1_gdsc {
status = "ok"
};
&hlos1_vote_turing_mmu_tbu0_gdsc {
status = "ok"
};
&hlos1_vote_turing_mmu_tbu1_gdsc {
status = "ok"
};
&cam_cc_titan_top_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&cam_cc_bps_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&cam_cc_ife_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&cam_cc_ife_1_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&cam_cc_ife_2_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&cam_cc_ipe_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&disp_cc_mdss_core_gdsc {
clocks = <&gcc GCC_DISP_AHB_CLK>;
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&gpu_cx_gdsc {
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&gpu_gx_gdsc {
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_GFX_LEVEL>;
qcom,retain-regs;
qcom,skip-disable-before-sw-enable;
status = "ok"
};
&video_cc_mvs0_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&video_cc_mvs0c_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&video_cc_mvs1_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
qcom,support-hw-trigger;
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&video_cc_mvs1c_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&qupv3_se5_i2c {
status = "ok"
nq@64 {
compatible = "rtc6226";
reg = <0x64>;
fmint-gpio = <&tlmm 50 0>;
vdd-supply = <&L11C>;
rtc6226,vdd-supply-voltage = <2800000 2800000>;
vio-supply = <&S10B>;
rtc6226,vio-supply-voltage = <1800000 1800000 >;
};
};
/* HS UART */
&qupv3_se15_4uart {
status = "ok"
};
#include "msm-rdbg.dtsi"
#include "camera/shima-camera.dtsi"
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