mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-12 01:51:34 -05:00
a5fa3d7646
Add USB nodes to support USB in peripheral mode on simulation platforms for Yupik. Change-Id: I5d73cde0fbcfb20eaa4fe578d9a65770c53965dc
68 lines
1.8 KiB
Devicetree
68 lines
1.8 KiB
Devicetree
#include <dt-bindings/clock/qcom,gcc-yupik.h>
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&soc {
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/* Primary USB port related controller */
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0xa600000 0x100000>;
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reg-names = "core_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
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<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 15 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"ss_phy_irq", "dm_hs_phy_irq";
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qcom,use-pdc-interrupts;
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USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk";
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0xa600000 0xcd00>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,is-utmi-l1-suspend;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis_u2_susphy_quirk;
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snps,ssp-u3-u0-quirk;
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tx-fifo-resize;
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maximum-speed = "super-speed";
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dr_mode = "otg";
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};
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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};
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