mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-12 01:51:34 -05:00
7d6bd23993
Add secure display heap configuration to enable secure memory allocations for secure display/camera usecases. Change-Id: I27132f3b1d85458fc9dc77d4969a42c5aa29ad09
1283 lines
28 KiB
Devicetree
1283 lines
28 KiB
Devicetree
#include <dt-bindings/clock/qcom,aop-qmp.h>
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#include <dt-bindings/clock/qcom,camcc-yupik.h>
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#include <dt-bindings/clock/qcom,dispcc-yupik.h>
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#include <dt-bindings/clock/qcom,gcc-yupik.h>
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#include <dt-bindings/clock/qcom,gpucc-yupik.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,videocc-yupik.h>
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#include <dt-bindings/interconnect/qcom,epss-l3.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,yupik.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Qualcomm Technologies, Inc. Yupik";
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compatible = "qcom,yupik";
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qcom,msm-id = <475 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases {
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ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
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};
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firmware: firmware {
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scm {
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compatible = "qcom,scm";
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};
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android {
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compatible = "android,firmware";
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vbmeta {
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compatible = "android,vbmeta";
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parts = "vbmeta,boot,system,vendor,dtbo";
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};
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fstab {
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compatible = "android,fstab";
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vendor {
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compatible = "android,vendor";
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dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
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type = "ext4";
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mnt_flags = "ro,barrier=1,discard";
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fsmgr_flags = "wait,slotselect,avb";
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status = "ok"
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};
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};
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};
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: hyp@80000000 {
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no-map;
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reg = <0x0 0x80000000 0x0 0x600000>;
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};
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xbl_aop_mem: xbl_aop_mem@80700000 {
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no-map;
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reg = <0x0 0x80700000 0x0 0x160000>;
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};
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cmd_db: cmd_db@80860000 {
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compatible = "qcom,cmd-db";
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no-map;
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reg = <0x0 0x80860000 0x0 0x20000>;
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};
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reserved_xbl_uefi: reserved_xbl_uefi@80880000 {
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no-map;
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reg = <0x0 0x80880000 0x0 0x14000>;
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};
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secdata_apss_mem: secdata_apss@808ff000 {
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no-map;
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reg = <0x0 0x808ff000 0x0 0x1000>;
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};
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smem_mem: smem@80900000 {
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no-map;
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reg = <0x0 0x80900000 0x0 0x200000>;
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};
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fw_mem: fw@80b00000 {
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no-map;
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reg = <0x0 0x80b00000 0x0 0x100000>;
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};
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wlan_fw_mem: wlan_fw@80c00000 {
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no-map;
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reg = <0x0 0x80c00000 0x0 0xc00000>;
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};
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cdsp_secure_heap_mem: cdsp_secure_heap@81800000 {
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no-map;
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reg = <0x0 0x81800000 0x0 0x1e00000>;
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};
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pil_cvp_mem: camera@86200000 {
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no-map;
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reg = <0x0 0x86200000 0x0 0x500000>;
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};
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pil_adsp_mem: adsp@86700000 {
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no-map;
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reg = <0x0 0x86700000 0x0 0x2800000>;
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};
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pil_cdsp_mem: cdsp@88f00000 {
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no-map;
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reg = <0x0 0x88f00000 0x0 0x1e00000>;
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};
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pil_camera_mem: video@8ad00000 {
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no-map;
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reg = <0x0 0x8ad00000 0x0 0x500000>;
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};
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pil_video_mem: cvp@8b200000 {
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no-map;
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reg = <0x0 0x8b200000 0x0 0x500000>;
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};
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pil_ipa_fw_mem: ipa_fw@8b700000 {
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no-map;
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reg = <0x0 0x8b700000 0x0 0x10000>;
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};
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pil_ipa_gsi_mem: ipa_gsi@8b710000 {
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no-map;
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reg = <0x0 0x8b710000 0x0 0xa000>;
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};
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pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 {
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no-map;
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reg = <0x0 0x8b71a000 0x0 0x2000>;
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};
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pil_mpss_mem: mpss@8b800000 {
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no-map;
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reg = <0x0 0x8b800000 0x0 0xf600000>;
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};
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pil_wpss_mem: wlan@9ae00000 {
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no-map;
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reg = <0x0 0x9ae00000 0x0 0x1900000>;
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};
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removed_mem: removed_region@c0000000 {
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no-map;
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reg = <0x0 0xc0000000 0x0 0x5100000>;
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};
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secure_display_memory: secure_display_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x00000000 0 0xffffffff>;
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reusable;
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alignment = <0 0x400000>;
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size = <0 0x8c00000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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soc: soc { };
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chosen {
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bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17a00000 0x10000>, /* GICD */
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<0x17a60000 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,yupik-pdc";
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reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
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qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
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<55 306 4>, <59 312 3>, <62 374 2>,
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<64 434 2>, <66 438 3>, <69 86 1>,
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<70 520 54>, <124 609 31>, <155 63 1>,
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<156 716 12>;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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wdog: qcom,wdt@17c10000 {
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compatible = "qcom,msm-watchdog";
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reg = <0x17c10000 0x1000>;
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reg-names = "wdt-base";
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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ipcc_mproc: qcom,ipcc@408000 {
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compatible = "qcom,ipcc";
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reg = <0x408000 0x1000>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <19200000>;
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};
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memtimer: timer@17c20000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17c20000 0x1000>;
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clock-frequency = <19200000>;
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frame@17c21000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c21000 0x1000>,
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<0x17c22000 0x1000>;
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};
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frame@17c23000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c23000 0x1000>;
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status = "disabled";
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};
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frame@17c25000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c25000 0x1000>;
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status = "disabled";
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};
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frame@17c27000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c27000 0x1000>;
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status = "disabled";
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};
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frame@17c29000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c29000 0x1000>;
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status = "disabled";
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};
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frame@17c2b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c2b000 0x1000>;
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status = "disabled";
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};
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frame@17c2d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c2d000 0x1000>;
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status = "disabled";
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};
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};
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qcom,msm-imem@146aa000 {
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compatible = "qcom,msm-imem";
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reg = <0x146aa000 0x1000>;
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ranges = <0x0 0x146aa000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mem_dump_table@10 {
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compatible = "qcom,msm-imem-mem_dump_table";
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reg = <0x10 0x8>;
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};
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restart_reason@65c {
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compatible = "qcom,msm-imem-restart_reason";
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reg = <0x65c 0x4>;
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};
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dload_type@1c {
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compatible = "qcom,msm-imem-dload-type";
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reg = <0x1c 0x4>;
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};
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boot_stats@6b0 {
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compatible = "qcom,msm-imem-boot_stats";
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reg = <0x6b0 0x20>;
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};
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kaslr_offset@6d0 {
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compatible = "qcom,msm-imem-kaslr_offset";
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reg = <0x6d0 0xc>;
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};
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pil@94c {
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compatible = "qcom,msm-imem-pil";
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reg = <0x94c 0xc8>;
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};
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pil@6dc {
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compatible = "qcom,msm-imem-pil-disable-timeout";
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reg = <0x6dc 0x4>;
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};
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diag_dload@c8 {
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compatible = "qcom,msm-imem-diag-dload";
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reg = <0xc8 0xc8>;
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo-board {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <76800000>;
|
|
clock-output-names = "xo_board";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sleep_clk: sleep-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "sleep_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_0_pipe_clk: pcie-0-pipe-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_0_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
pcie_1_pipe_clk: pcie-1-pipe-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "pcie_1_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <1000>;
|
|
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
|
|
#clock-cells = <0>;
|
|
};
|
|
};
|
|
|
|
bi_tcxo: bi_tcxo {
|
|
compatible = "fixed-factor-clock";
|
|
clock-mult = <1>;
|
|
clock-div = <4>;
|
|
clocks = <&xo_board>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
bi_tcxo_ao: bi_tcxo_ao {
|
|
compatible = "fixed-factor-clock";
|
|
clock-mult = <1>;
|
|
clock-div = <4>;
|
|
clocks = <&xo_board>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
aopcc: qcom,aopcc {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "aopcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
rpmhcc: qcom,rpmhcc {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "rpmhcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "gcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
camcc: clock-controller@ad00000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "camcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "dispcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpucc: clock-controller@3d90000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "gpucc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
videocc: clock-controller@aaf0000 {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "videocc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
ufsphy_mem: ufsphy_mem@1d87000 {
|
|
reg = <0x1d87000 0xe00>;
|
|
reg-names = "phy_mem";
|
|
#phy-cells = <0>;
|
|
|
|
lanes-per-direction = <2>;
|
|
clock-names = "ref_clk_src",
|
|
"ref_clk",
|
|
"ref_aux_clk";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_1_CLKREF_EN>,
|
|
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
|
|
resets = <&ufshc_mem 0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ufshc_mem: ufshc@1d84000 {
|
|
compatible = "qcom,ufshc";
|
|
reg = <0x1d84000 0x3000>;
|
|
reg-names = "ufs_mem";
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&ufsphy_mem>;
|
|
phy-names = "ufsphy";
|
|
#reset-cells = <1>;
|
|
|
|
lanes-per-direction = <2>;
|
|
dev-ref-clk-freq = <0>; /* 19.2 MHz */
|
|
clock-names =
|
|
"core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"core_clk_ice",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk",
|
|
"rx_lane1_sync_clk";
|
|
clocks =
|
|
<&gcc GCC_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
|
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
|
freq-table-hz =
|
|
<75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<75000000 300000000>,
|
|
<75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
|
|
qcom,ufs-bus-bw,name = "ufshc_mem";
|
|
qcom,ufs-bus-bw,num-cases = <26>;
|
|
qcom,ufs-bus-bw,num-paths = <2>;
|
|
qcom,ufs-bus-bw,vectors-KBps =
|
|
/*
|
|
* During HS G3 UFS runs at nominal voltage corner, vote
|
|
* higher bandwidth to push other buses in the data path
|
|
* to run at nominal to achieve max throughput.
|
|
* 4GBps pushes BIMC to run at nominal.
|
|
* 200MBps pushes CNOC to run at nominal.
|
|
* Vote for half of this bandwidth for HS G3 1-lane.
|
|
* For max bandwidth, vote high enough to push the buses
|
|
* to run in turbo voltage corner.
|
|
*/
|
|
<0 0>, <0 0>, /* No vote */
|
|
<922 0>, <1000 0>, /* PWM G1 */
|
|
<1844 0>, <1000 0>, /* PWM G2 */
|
|
<3688 0>, <1000 0>, /* PWM G3 */
|
|
<7376 0>, <1000 0>, /* PWM G4 */
|
|
<1844 0>, <1000 0>, /* PWM G1 L2 */
|
|
<3688 0>, <1000 0>, /* PWM G2 L2 */
|
|
<7376 0>, <1000 0>, /* PWM G3 L2 */
|
|
<14752 0>, <1000 0>, /* PWM G4 L2 */
|
|
<127796 0>, <1000 0>, /* HS G1 RA */
|
|
<255591 0>, <1000 0>, /* HS G2 RA */
|
|
<2097152 0>, <102400 0>, /* HS G3 RA */
|
|
<4194304 0>, <204800 0>, /* HS G4 RA */
|
|
<255591 0>, <1000 0>, /* HS G1 RA L2 */
|
|
<511181 0>, <1000 0>, /* HS G2 RA L2 */
|
|
<4194304 0>, <204800 0>, /* HS G3 RA L2 */
|
|
<8388608 0>, <409600 0>, /* HS G4 RA L2 */
|
|
<149422 0>, <1000 0>, /* HS G1 RB */
|
|
<298189 0>, <1000 0>, /* HS G2 RB */
|
|
<2097152 0>, <102400 0>, /* HS G3 RB */
|
|
<4194304 0>, <204800 0>, /* HS G4 RB */
|
|
<298189 0>, <1000 0>, /* HS G1 RB L2 */
|
|
<596378 0>, <1000 0>, /* HS G2 RB L2 */
|
|
/* As UFS working in HS G3 RB L2 mode, aggregated
|
|
* bandwidth (AB) should take care of providing
|
|
* optimum throughput requested. However, as tested,
|
|
* in order to scale up CNOC clock, instantaneous
|
|
* bindwidth (IB) needs to be given a proper value too.
|
|
*/
|
|
<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
|
|
<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
|
|
<7643136 0>, <307200 0>; /* Max. bandwidth */
|
|
|
|
qcom,bus-vector-names = "MIN",
|
|
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
|
|
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
|
|
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
|
|
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
|
|
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
|
|
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
|
|
"MAX";
|
|
|
|
reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
|
|
resets = <&gcc GCC_UFS_PHY_BCR>;
|
|
reset-names = "rst";
|
|
|
|
rpm-level = <3>;
|
|
spm-level = <3>;
|
|
|
|
status = "disabled";
|
|
|
|
qos0 {
|
|
mask = <0xf0>;
|
|
vote = <59>;
|
|
};
|
|
|
|
qos1 {
|
|
mask = <0x0f>;
|
|
vote = <65>;
|
|
};
|
|
};
|
|
|
|
clk_virt: interconnect {
|
|
compatible = "qcom,yupik-clk_virt";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
config_noc: interconnect@1500000 {
|
|
compatible = "qcom,yupik-config_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
mc_virt: interconnect@1580000 {
|
|
compatible = "qcom,yupik-mc_virt";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
system_noc: interconnect@1680000 {
|
|
compatible = "qcom,yupik-system_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
aggre1_noc: interconnect@16e0000 {
|
|
compatible = "qcom,yupik-aggre1_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
aggre2_noc: interconnect@1700000 {
|
|
compatible = "qcom,yupik-aggre2_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
mmss_noc: interconnect@1740000 {
|
|
compatible = "qcom,yupik-mmss_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
lpass_ag_noc: interconnect@3c40000 {
|
|
compatible = "qcom,yupik-lpass_ag_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
dc_noc: interconnect@90e0000 {
|
|
compatible = "qcom,yupik-dc_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
gem_noc: interconnect@9100000 {
|
|
compatible = "qcom,yupik-gem_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
nsp_noc: interconnect@a0c0000 {
|
|
compatible = "qcom,yupik-nsp_noc";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
epss_l3_cpu: l3_cpu@18590000 {
|
|
compatible = "qcom,yupik-epss-l3-cpu";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x18200000 0x10000>,
|
|
<0x18210000 0x10000>,
|
|
<0x18220000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>,
|
|
<CONTROL_TCS 0>;
|
|
|
|
system_pm {
|
|
compatible = "qcom,system-pm";
|
|
};
|
|
};
|
|
|
|
disp_rsc: rsc@af20000 {
|
|
label = "disp_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xaf20000 0x10000>;
|
|
reg-names = "drv-0";
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0x1c00>;
|
|
qcom,drv-id = <0>;
|
|
qcom,tcs-config = <ACTIVE_TCS 0>,
|
|
<SLEEP_TCS 1>,
|
|
<WAKE_TCS 1>,
|
|
<CONTROL_TCS 0>;
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
tcsr: syscon@1fc0000 {
|
|
compatible = "syscon";
|
|
reg = <0x1fc0000 0x30000>;
|
|
};
|
|
|
|
smem: qcom,smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_mem>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
qcom,smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_SMP2P>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
adsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
adsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-nsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <94>, <432>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <5>;
|
|
|
|
cdsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
cdsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-wpss {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <617>, <616>;
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <13>;
|
|
|
|
wpss_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
wpss_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,glink {
|
|
compatible = "qcom,glink";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
glink_modem: modem {
|
|
qcom,remote-pid = <1>;
|
|
transport = "smem";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "mpss_smem";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_MPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "modem";
|
|
qcom,glink-label = "mpss";
|
|
|
|
qcom,modem_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,low-latency;
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,modem_ds {
|
|
qcom,glink-channels = "DS";
|
|
qcom,intents = <0x4000 0x2>;
|
|
};
|
|
|
|
qcom,modem_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_adsp>,
|
|
<&glink_wpss>;
|
|
};
|
|
};
|
|
|
|
glink_adsp: adsp {
|
|
qcom,remote-pid = <2>;
|
|
transport = "smem";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "adsp_smem";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "adsp";
|
|
qcom,glink-label = "lpass";
|
|
|
|
qcom,adsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,adsp_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_modem>,
|
|
<&glink_cdsp>,
|
|
<&glink_wpss>;
|
|
};
|
|
};
|
|
|
|
glink_cdsp: cdsp {
|
|
qcom,remote-pid = <5>;
|
|
transport = "smem";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "dsps_smem";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "cdsp";
|
|
qcom,glink-label = "cdsp";
|
|
|
|
qcom,cdsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,cdsp_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_adsp>,
|
|
<&glink_wpss>;
|
|
};
|
|
};
|
|
|
|
glink_wpss: wpss {
|
|
qcom,remote-pid = <13>;
|
|
transport = "smem";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "wpss_smem";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_WPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "wpss";
|
|
qcom,glink-label = "wpss";
|
|
|
|
qcom,wpss_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,wpss_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_modem>,
|
|
<&glink_adsp>,
|
|
<&glink_cdsp>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-apr-apps2 {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "apr_apps2";
|
|
qcom,glinkpkt-dev-name = "apr_apps2";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop@c300000 {
|
|
compatible = "qcom,qmp-mbox";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "aop_qmp";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
reg = <0xc300000 0x400>;
|
|
reg-names = "msgram";
|
|
|
|
label = "aop";
|
|
qcom,early-boot;
|
|
priority = <0>;
|
|
mbox-desc-offset = <0x0>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
aop-msg-client {
|
|
compatible = "qcom,debugfs-qmp-client";
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "aop";
|
|
};
|
|
|
|
qcom-secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
};
|
|
};
|
|
|
|
#include "shima-gdsc.dtsi"
|
|
#include "yupik-pinctrl.dtsi"
|
|
#include "yupik-pm.dtsi"
|
|
#include "yupik-stub-regulator.dtsi"
|
|
|
|
&gcc_pcie_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&gcc_pcie_1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&gcc_ufs_phy_gdsc {
|
|
compatible = "regulator-fixed";
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&gcc_usb30_prim_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&gcc_usb30_sec_gdsc {
|
|
compatible = "regulator-fixed";
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&cam_cc_titan_top_gdsc {
|
|
compatible = "regulator-fixed";
|
|
reg = <0xad0c194 0x4>;
|
|
status = "ok"
|
|
};
|
|
|
|
&cam_cc_bps_gdsc {
|
|
compatible = "regulator-fixed";
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&cam_cc_ife_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&cam_cc_ife_1_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&cam_cc_ife_2_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&cam_cc_ipe_0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&disp_cc_mdss_core_gdsc {
|
|
compatible = "regulator-fixed";
|
|
reg = <0xaf01004 0x4>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&gpu_cx_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&gpu_gx_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
&video_cc_mvs0_gdsc {
|
|
compatible = "regulator-fixed";
|
|
reg = <0xaaf3004 0x4>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok"
|
|
};
|
|
|
|
&video_cc_mvsc_gdsc {
|
|
compatible = "regulator-fixed";
|
|
status = "ok"
|
|
};
|
|
|
|
#include "yupik-usb.dtsi"
|
|
#include "yupik-ion.dtsi"
|
|
#include "msm-arm-smmu-yupik.dtsi"
|
|
#include "yupik-qupv3.dtsi"
|