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23fe31dedb
In previous MediaTek PLL design, it assumes the pcw change control is always on the CON1 register. However, the pcw change bit on MT8183 was moved onto CON0 because the the PCW length of audio PLLs are extended to 32-bit. Add configurable pcw_chg_reg to set the pcw change control register address or using the default control register CON1 if without setting in pll data. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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| README | ||
Linux kernel
============
There are several guides for kernel developers and users. These guides can
be rendered in a number of formats, like HTML and PDF. Please read
Documentation/admin-guide/README.rst first.
In order to build the documentation, use ``make htmldocs`` or
``make pdfdocs``. The formatted documentation can also be read online at:
https://www.kernel.org/doc/html/latest/
There are various text files in the Documentation/ subdirectory,
several of them using the Restructured Text markup notation.
Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
the problems which may result by upgrading your kernel.