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Filename	Latest commit message	Latest commit date
Ritesh Kumar 272f660e76 disp: pll: Fix cfg1 value when pclk_src_mux parent is updated ... Currently, PLL_CFG1(1:0) register is updated with cached values in dsi_pll_enable. This can create issue when UEFI and kernel cfg1 programming is not same. To fix it, return cached value of cfg1 when its read in pclk_mux_read, so that pclk_mux_write is called and cached value is updated. This fix is for 10nm pll. Change-Id: I8465cb9027a1639f3cdeb02274513ac680f84632 Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>		2021-08-12 04:08:13 -07:00
config	display: msm: qpic: Add QPIC display support base on DRM framework	2021-06-20 22:18:43 -07:00
hdcp	disp: msm: make msm_drm as module for GKI	2020-04-28 15:52:49 -07:00
include	disp: msm: parse SPMI registers and append to IO lend list	2020-08-17 09:47:28 -07:00
msm	disp: pll: Fix cfg1 value when pclk_src_mux parent is updated	2021-08-12 04:08:13 -07:00
rotator	disp: rotator: add rev checks for rotator for blair target	2021-05-21 12:13:30 +05:30
tinydrm	display: msm: qpic: Add QPIC display support base on DRM framework	2021-06-20 22:18:43 -07:00
Android.bp	display: get unifdef explicitly	2021-04-02 12:26:40 +05:30
display_kernel_headers.py	display: get unifdef explicitly	2021-04-02 12:26:40 +05:30
Makefile	display: msm: qpic: Add QPIC display support base on DRM framework	2021-06-20 22:18:43 -07:00
NOTICE	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00