mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-11-08 11:45:53 -05:00
cb1c36fc87
Add support for SM8325 platform for the MSM and APQ variants. Change-Id: If5dbbbec42ca4b51067173fab69496ef504fac14
348 lines
8 KiB
Devicetree
348 lines
8 KiB
Devicetree
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,dispcc-lahaina.h>
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#include <dt-bindings/clock/qcom,gcc-lahaina.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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/ {
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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qcom,msm-id = <415 0x10000>, <501 0x10000>;
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interrupt-parent = <&vgic>;
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qcom-mem-buf {
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compatible = "qcom,mem-buf";
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qcom,mem-buf-capabilities = "consumer";
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};
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chosen {
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bootargs = "nokaslr log_buf_len=256K root=/dev/ram rw init=/init console=hvc0 loglevel=8";
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linux,initrd-start = <0x2a900000>;
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linux,initrd-end = <0x2b100000>; /* 8 MB */
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kaslr-seed = <0xfeedbeef 0xc0def00d>;
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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CPU0: cpu@0 {
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN
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&CLUSTER_PWR_DWN>;
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};
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CPU1: cpu@100 {
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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cpu-idle-states = <&CPU_PWR_DWN
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&CLUSTER_PWR_DWN>;
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};
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};
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idle-states {
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CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <702>;
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exit-latency-us = <1061>;
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min-residency-us = <4488>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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CLUSTER_PWR_DWN: d4 { /* C4+D4 */
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compatible = "arm,idle-state";
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idle-state-name = "l3-pc";
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entry-latency-us = <2752>;
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exit-latency-us = <3048>;
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min-residency-us = <6118>;
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arm,psci-suspend-param = <0x40000044>;
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local-timer-stop;
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};
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};
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neuron-client-block {
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compatible = "qcom,neuron-service";
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#address-cells = <1>;
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#size-cells = <0>;
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protocol {
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compatible = "qcom,neuron-protocol-block";
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processes = "client";
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};
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application {
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compatible = "qcom,neuron-block-client";
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};
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channel@0 {
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reg = <0>;
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compatible = "qcom,neuron-channel-haven-shmem";
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class = "message-queue";
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direction = "send";
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max-size = <0 65536>;
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haven-label = <1>;
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};
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channel@1 {
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reg = <1>;
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compatible = "qcom,neuron-channel-haven-shmem";
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class = "message-queue";
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direction = "receive";
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max-size = <0 65536>;
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haven-label = <2>;
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};
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};
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qrtr-haven {
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compatible = "qcom,qrtr-haven";
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haven-label = <3>;
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};
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qcom,vm-config {
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compatible = "qcom,vm-1.0";
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vm-type = "aarch64-guest";
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boot-config = "fdt,unified";
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os-type = "linux";
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kernel-entry-segment = "kernel";
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kernel-entry-offset = <0x0 0x0>;
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vendor = "Qualcomm";
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image-name = "qcom,trustedvm";
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qcom,pasid = <0x0 0x1c>;
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iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0
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0x0 0xc400000 0x0 0xc400000 0x0 0x30000 0x1
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0x0 0xc440000 0x0 0xc440000 0x0 0x10000 0x1
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0x0 0xe600000 0x0 0xe600000 0x0 0x100000 0x1
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0x0 0xe700000 0x0 0xe700000 0x0 0xa0000 0x1
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0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;
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gic-irq-ranges = <283 283>; /* PVM->SVM IRQ transfer */
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memory {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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base-address = <0x0 0xD0800000>;
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size-min = <0x0 0x76f7000>; /* 118 MB */
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};
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segments {
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ramdisk = <2>; /* 8MB */
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};
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vcpus {
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config = "/cpus";
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affinity = "static";
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affinity-map = <0x4 0x5>;
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sched-priority = <0>; /* relative to PVM */
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sched-timeslice = <2000>; /* in ms */
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};
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interrupts {
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config = &vgic;
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};
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vdevices {
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generate = "/hypervisor";
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rm-rpc {
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vdevice-type = "rm-rpc";
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generate = "/hypervisor/qcom,resource-mgr";
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console-dev;
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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qcom,label = <0x1>;
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};
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mem-buf-message-queue-pair {
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vdevice-type = "message-queue-pair";
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generate = "/hypervisor/membuf-msgq-pair";
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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peer-default;
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qcom,label = <0x0000001>;
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};
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display-message-queue-pair {
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vdevice-type = "message-queue-pair";
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generate = "/hypervisor/display-msgq-pair";
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message-size = <0x000000f0>;
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queue-depth = <0x00000008>;
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peer-default;
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qcom,label = <0x0000002>;
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};
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neuron-ch1-shm {
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vdevice-type = "shm-doorbell";
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generate = "/hypervisor/neuron-ch1-shm";
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push-compatible = "qcom,neuron-channel-haven-shmem-gen";
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peer-default;
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memory {
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qcom,label = <0x1>;
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allocate-base;
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};
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};
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neuron-ch2-shm {
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vdevice-type = "shm-doorbell";
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generate = "/hypervisor/neuron-ch2-shm";
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push-compatible = "qcom,neuron-channel-haven-shmem-gen";
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peer-default;
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memory {
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qcom,label = <0x2>;
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allocate-base;
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};
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};
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qrtr-shm {
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vdevice-type = "shm-doorbell";
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generate = "/hypervisor/qrtr-shm";
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push-compatible = "qcom,qrtr-haven-gen";
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peer-default;
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memory {
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qcom,label = <0x3>;
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allocate-base;
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};
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};
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};
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};
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firmware: firmware {
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scm {
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compatible = "qcom,scm";
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};
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};
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soc: soc { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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spmi_bus: qcom,spmi@c440000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0xc440000 0x1100>,
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<0xc600000 0x2000000>,
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<0xe600000 0x100000>,
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<0xe700000 0xa0000>,
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<0xc40a000 0x26000>;
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reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
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#address-cells = <2>;
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#size-cells = <0>;
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cell-index = <0>;
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qcom,channel = <0>;
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qcom,ee = <0>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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vgic: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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interrupt-controller;
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#interrupt-cells = <0x3>;
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reg = <0x17a00000 0x10000>, /* GICD */
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<0x17a60000 0x100000>; /* GICR * 8 */
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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always-on;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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/*
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* QUPv3 Instances
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* North 4 : SE 4
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*/
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/* QUPv3_0 wrapper instance: North QUP */
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qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
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compatible = "qcom,qupv3-geni-se";
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reg = <0x9c0000 0x2000>;
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};
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/* GPI */
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gpi_dma0: qcom,gpi-dma@900000 {
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compatible = "qcom,gpi-dma";
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#dma-cells = <5>;
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reg = <0x900000 0x60000>;
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reg-names = "gpi-top";
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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qcom,max-num-gpii = <12>;
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qcom,gpii-mask = <0x80>;
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qcom,ev-factor = <2>;
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qcom,gpi-ee-offset = <0x10000>;
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qcom,le-vm;
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status = "ok"
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};
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/* I2C SE */
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qupv3_se4_i2c: i2c@990000 {
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compatible = "qcom,i2c-geni";
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reg = <0x990000 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&gpi_dma0 0 4 3 64 0>,
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<&gpi_dma0 1 4 3 64 0>;
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dma-names = "tx", "rx";
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qcom,wrapper-core = <&qupv3_0>;
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qcom,le-vm;
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status = "ok"
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};
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qupv3_se4_spi: spi@990000 {
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compatible = "qcom,spi-geni";
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reg = <0x990000 0x4000>;
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reg-names = "se_phys";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&gpi_dma0 0 4 1 64 0>,
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<&gpi_dma0 1 4 1 64 0>;
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dma-names = "tx", "rx";
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spi-max-frequency = <50000000>;
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qcom,wrapper-core = <&qupv3_0>;
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qcom,le-vm;
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status = "disabled";
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};
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qcom_smcinvoke {
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compatible = "qcom,smcinvoke";
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};
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qtee_shmbridge {
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compatible = "qcom,tee-shared-memory-bridge";
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qcom,support-hypervisor;
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};
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};
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#include "lahaina-vm-ion.dtsi"
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#include "display/trustedvm-lahaina-sde.dtsi"
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#include "display/trustedvm-lahaina-sde-display.dtsi"
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#include "display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"
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#include "display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi"
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#include "display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi"
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#include "display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi"
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