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android_kernel_motorola_sm6375/qcom/sa6155.dtsi
Vinay Sudra 2ae21b046f ARM: dts: msm: Add aop_send_message device node interface for SA6155 
Add aop_send_message debugfs interface for clients to send data to the AOP.

Change-Id: Iabda57871d389e2e509d5ad526996baf95761a2d
2021-05-27 14:33:10 +05:30

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#include "sm6150.dtsi"
#include "sa6155-pmic.dtsi"
#include "display/sa6155-display.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SA6155";
compatible = "qcom,sa6155";
qcom,msm-name = "SA6155";
qcom,msm-id = <384 0x10000>;
aliases {
pci-domain0 = &pcie0; /* PCIe0 domain */
};
};
&reserved_memory {
/* wlan_msa_mem is only used when iHelium is attached,
* so remove the node for sa6155
*/
/delete-node/ wlan_msa_mem;
};
&soc {
qfprom: qfprom@780130 {
compatible = "qcom,qfprom";
reg = <0x00780130 0x4>;
#address-cells = <1>;
#size-cells = <1>;
read-only;
ranges;
};
aop-msg-client {
compatible = "qcom,debugfs-qmp-client";
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
};
};
&qusb_phy0 {
vdd-supply = <&L5A>;
vdda18-supply = <&L12A>;
vdda33-supply = <&L13A>;
};
&usb_qmp_phy {
vdd-supply = <&L5A>;
core-supply = <&L12A>;
};
&qusb_phy1 {
vdd-supply = <&L5A>;
vdda18-supply = <&L12A>;
vdda33-supply = <&L13A>;
};
&gcc {
compatible = "qcom,sa6155-gcc", "syscon";
/delete-property/ protected-clocks;
};
&camcc {
compatible = "qcom,sa6155-camcc", "syscon";
vdd_mx-supply = <&VDD_CX_LEVEL>;
};
&dispcc {
compatible = "qcom,sa6155-dispcc", "syscon";
};
&gpucc {
compatible = "qcom,sa6155-gpucc", "syscon";
vdd_mx-supply = <&VDD_CX_LEVEL>;
};
&scc {
vdd_cx-supply = <&VDD_CX_LEVEL>;
status = "ok"
};
&videocc {
compatible = "qcom,sa6155-videocc", "syscon";
};
&thermal_zones {
cpuss-0-step {
trips {
cpu45-config {
temperature = <115000>;
};
};
};
cpuss-1-step {
trips {
cpu23-config {
temperature = <115000>;
};
};
};
cpuss-2-step {
trips {
cpu01-config {
temperature = <115000>;
};
};
};
cpu-1-0-step {
trips {
cpu6-0-config {
temperature = <115000>;
};
};
};
cpu-1-1-step {
trips {
cpu6-1-config {
temperature = <115000>;
};
};
};
cpu-1-2-step {
trips {
cpu7-0-config {
temperature = <115000>;
};
};
};
cpu-1-3-step {
trips {
cpu7-1-config {
temperature = <115000>;
};
};
};
gpu-step {
trips {
gpu-trip {
temperature = <105000>;
};
gpu-cx-mon {
temperature = <110000>;
};
};
};
q6-hvx-step {
trips {
q6-hvx-config {
temperature = <105000>;
};
q6-hvx-trip1 {
temperature = <105000>;
};
q6-hvx-cx-mon {
temperature = <110000>;
};
};
};
mdm-core-step {
trips {
mdm-core-cx-mon {
temperature = <110000>;
};
};
};
camera-step {
trips {
camera-cx-mon {
temperature = <110000>;
};
};
};
wlan-step {
trips {
wlan-cx-mon {
temperature = <110000>;
};
};
};
display-step {
trips {
display-cx-mon {
temperature = <110000>;
};
};
};
video-step {
trips {
video-cx-mon {
temperature = <110000>;
};
};
};
};
&reserved_memory {
uefi_log: uefi_log@9241C000 {
reg = <0x0 0x9241C000 0x0 0x10000>;
label = "uefi_log";
};
};
#include "sa6155-pcie.dtsi"
&slpi_tlmm {
status = "ok"
};
/* GPU power level overrides */
&msm_gpu {
/*
* Speed-bin zero is default speed bin.
* For rest of the speed bins, speed-bin value
* is calulated as FMAX/4.8 MHz round up to zero
* decimal places.
*/
/delete-node/qcom,gpu-pwrlevel-bins;
qcom,gpu-pwrlevel-bins {
#address-cells = <1>;
#size-cells = <0>;
compatible="qcom,gpu-pwrlevel-bins";
qcom,gpu-pwrlevels-0 {
#address-cells = <1>;
#size-cells = <0>;
qcom,speed-bin = <0>;
qcom,initial-pwrlevel = <4>;
qcom,ca-target-pwrlevel = <3>;
/* TURBO */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <845000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <11>;
qcom,bus-min = <10>;
qcom,bus-max = <11>;
};
/* NOM L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <745000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <10>;
qcom,bus-min = <9>;
qcom,bus-max = <11>;
};
/* NOM */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <650000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <9>;
qcom,bus-min = <8>;
qcom,bus-max = <10>;
};
/* SVS L1 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
};
/* SVS */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <435000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <8>;
};
/* XO */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <0>;
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
qcom,bus-freq = <0>;
qcom,bus-min = <0>;
qcom,bus-max = <0>;
};
};
qcom,gpu-pwrlevels-1 {
#address-cells = <1>;
#size-cells = <0>;
qcom,speed-bin = <177>;
qcom,initial-pwrlevel = <4>;
qcom,ca-target-pwrlevel = <3>;
/* TURBO */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <845000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <11>;
qcom,bus-min = <10>;
qcom,bus-max = <11>;
};
/* NOM L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <745000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <10>;
qcom,bus-min = <9>;
qcom,bus-max = <11>;
};
/* NOM */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <650000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <9>;
qcom,bus-min = <8>;
qcom,bus-max = <10>;
};
/* SVS L1 */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
};
/* SVS */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <435000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <8>;
};
/* XO */
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <0>;
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
qcom,bus-freq = <0>;
qcom,bus-min = <0>;
qcom,bus-max = <0>;
};
};
qcom,gpu-pwrlevels-2 {
#address-cells = <1>;
#size-cells = <0>;
qcom,speed-bin = <156>;
qcom,initial-pwrlevel = <3>;
qcom,ca-target-pwrlevel = <2>;
/* NOM L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <745000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <11>;
qcom,bus-min = <10>;
qcom,bus-max = <11>;
};
/* NOM */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <650000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <9>;
qcom,bus-min = <8>;
qcom,bus-max = <10>;
};
/* SVS L1 */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
};
/* SVS */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <435000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <8>;
};
/* XO */
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <0>;
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
qcom,bus-freq = <0>;
qcom,bus-min = <0>;
qcom,bus-max = <0>;
};
};
qcom,gpu-pwrlevels-3 {
#address-cells = <1>;
#size-cells = <0>;
qcom,speed-bin = <136>;
qcom,initial-pwrlevel = <2>;
qcom,ca-target-pwrlevel = <1>;
/* NOM */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <650000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <9>;
qcom,bus-min = <8>;
qcom,bus-max = <10>;
};
/* SVS L1 */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
};
/* SVS */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <435000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <8>;
};
/* XO */
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <0>;
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
qcom,bus-freq = <0>;
qcom,bus-min = <0>;
qcom,bus-max = <0>;
};
};
qcom,gpu-pwrlevels-4 {
#address-cells = <1>;
#size-cells = <0>;
qcom,speed-bin = <105>;
qcom,initial-pwrlevel = <1>;
qcom,ca-target-pwrlevel = <0>;
/* SVS L1 */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <500000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <7>;
qcom,bus-max = <9>;
};
/* SVS */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <435000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <8>;
};
/* XO */
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <0>;
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
qcom,bus-freq = <0>;
qcom,bus-min = <0>;
qcom,bus-max = <0>;
};
};
qcom,gpu-pwrlevels-5 {
#address-cells = <1>;
#size-cells = <0>;
qcom,speed-bin = <73>;
qcom,initial-pwrlevel = <0>;
qcom,ca-target-pwrlevel = <0>;
/* SVS */
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <350000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <7>;
qcom,bus-min = <5>;
qcom,bus-max = <8>;
};
/* XO */
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <0>;
qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;
qcom,bus-freq = <0>;
qcom,bus-min = <0>;
qcom,bus-max = <0>;
};
};
};
};
&mdss_dsi0_pll {
/delete-property/ qcom,dsi-pll-ssc-en;
};
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