A-Team_Digital_Solutions/android_kernel_motorola_sm6375
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android_kernel_motorola_sm6375/qcom/yupik.dtsi
Priyansh Jain 22d1e081df ARM: dts: qcom: Add cooling cells property in all the CPU node for yupik 
Add coolings cells property for all the CPU devicetree node for
yupik, as for qultivate variant any two of the CPU cores can be fused
out, So, remaining gold cores can be mitigated.

Change-Id: Iccf902818f1d8587ff9b88b725817ff0d5d2ee0e
2023-04-17 00:52:15 -07:00

5557 lines
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#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/clock/qcom,camcc-yupik.h>
#include <dt-bindings/clock/qcom,dispcc-yupik.h>
#include <dt-bindings/clock/qcom,gcc-yupik.h>
#include <dt-bindings/clock/qcom,gpucc-yupik.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-yupik.h>
#include <dt-bindings/interconnect/qcom,epss-l3.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,yupik.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,dcc_v2.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
opp-supported-hw = <ddrtype>;}
#define DDR_TYPE_LPDDR4X 7
#define DDR_TYPE_LPDDR5 8
/ {
model = "Qualcomm Technologies, Inc. Yupik";
compatible = "qcom,yupik";
qcom,msm-id = <475 0x10000>, <515 0x10000>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen {
bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
};
memory { device_type = "memory"; reg = <0 0 0 0>; };
reserved_memory: reserved-memory { };
mem-offline {
compatible = "qcom,mem-offline";
offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
<0x1 0xc0000000 0x0 0x80000000>,
<0x2 0xc0000000 0x1 0x40000000>;
granule = <512>;
mboxes = <&qmp_aop 0>;
};
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/
sdhc1 = &sdhc_2; /* SDC2 SD card slot */
serial0 = &qupv3_se5_2uart;
hsuart0 = &qupv3_se7_4uart;
swr0 = &swr0;
swr1 = &swr1;
swr2 = &swr2;
};
firmware: firmware {};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-level = <3>;
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
next-level-cache = <&L2_3>;
#cooling-cells = <2>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
next-level-cache = <&L2_4>;
#cooling-cells = <2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
next-level-cache = <&L2_5>;
#cooling-cells = <2>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <520>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
next-level-cache = <&L2_6>;
#cooling-cells = <2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>;
capacity-dmips-mhz = <1985>;
dynamic-power-coefficient = <552>;
qcom,freq-domain = <&cpufreq_hw 2 4>;
next-level-cache = <&L2_7>;
#cooling-cells = <2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
};
cluster2 {
core0 {
cpu = <&CPU7>;
};
};
};
};
sram: sram@18509400 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "mmio-sram";
no-memory-wc;
reg = <0x0 0x18509400 0x0 0x400>;
ranges = <0x0 0x0 0x0 0x18509400 0x0 0x400>;
cpu_scp_lpri: scp-shmem@0 {
compatible = "arm,scp-shmem";
reg = <0x0 0x0 0x0 0x80>;
};
};
soc: soc { };
};
&firmware {
scm {
compatible = "qcom,scm";
qcom,dload-mode = <&tcsr 0x13000>;
};
android {
compatible = "android,firmware";
vbmeta {
compatible = "android,vbmeta";
parts = "vbmeta,boot,system,vendor,dtbo";
};
fstab {
compatible = "android,fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait,slotselect,avb";
status = "ok"
};
};
};
};
&reserved_memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
hyp_mem: hyp@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0x600000>;
};
xbl_aop_mem: xbl_aop_mem@80700000 {
no-map;
reg = <0x0 0x80700000 0x0 0x160000>;
};
cmd_db: cmd_db@80860000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x0 0x80860000 0x0 0x20000>;
};
reserved_xbl_uefi: reserved_xbl_uefi@80880000 {
no-map;
reg = <0x0 0x80880000 0x0 0x14000>;
};
secdata_apss_mem: secdata_apss@808ff000 {
no-map;
reg = <0x0 0x808ff000 0x0 0x1000>;
};
smem_mem: smem@80900000 {
no-map;
reg = <0x0 0x80900000 0x0 0x200000>;
};
fw_mem: fw@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
wlan_fw_mem: wlan_fw@80c00000 {
no-map;
reg = <0x0 0x80c00000 0x0 0xc00000>;
};
cdsp_secure_heap_mem: cdsp_secure_heap@81800000 {
no-map;
reg = <0x0 0x81800000 0x0 0x1e00000>;
};
pil_cvp_mem: camera@86200000 {
no-map;
reg = <0x0 0x86200000 0x0 0x500000>;
};
pil_adsp_mem: adsp@86700000 {
no-map;
reg = <0x0 0x86700000 0x0 0x2800000>;
};
pil_cdsp_mem: cdsp@88f00000 {
no-map;
reg = <0x0 0x88f00000 0x0 0x1e00000>;
};
adsp_mem: adsp_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0xC00000>;
};
pil_camera_mem: video@8ad00000 {
no-map;
reg = <0x0 0x8ad00000 0x0 0x500000>;
};
pil_video_mem: cvp@8b200000 {
no-map;
reg = <0x0 0x8b200000 0x0 0x500000>;
};
pil_ipa_fw_mem: ipa_fw@8b700000 {
no-map;
reg = <0x0 0x8b700000 0x0 0x10000>;
};
pil_ipa_gsi_mem: ipa_gsi@8b710000 {
no-map;
reg = <0x0 0x8b710000 0x0 0xa000>;
};
pil_gpu_micro_code_mem: gpu_micro_code@8b71a000 {
no-map;
reg = <0x0 0x8b71a000 0x0 0x2000>;
};
pil_mpss_mem: mpss@8b800000 {
no-map;
reg = <0x0 0x8b800000 0x0 0xf600000>;
};
pil_wpss_mem: wlan@9ae00000 {
no-map;
reg = <0x0 0x9ae00000 0x0 0x1900000>;
};
removed_mem: removed_region@c0000000 {
no-map;
reg = <0x0 0xc0000000 0x0 0x5100000>;
};
pil_trustedvm_mem: pil_trustedvm_region@d0800000 {
no-map;
reg = <0x0 0xd0800000 0x0 0x76f7000>;
};
qrtr_shbuf: qrtr-shmem {
no-map;
reg = <0x0 0xd7ef7000 0x0 0x9000>;
};
chan0_shbuf: neuron_block@0 {
no-map;
reg = <0x0 0xd7f00000 0x0 0x80000>;
};
chan1_shbuf: neuron_block@1 {
no-map;
reg = <0x0 0xd7f80000 0x0 0x80000>;
};
user_contig_mem: user_contig_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
qseecom_mem: qseecom_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
non_secure_display_memory: non_secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x6400000>;
};
splash_memory:splash_region {
reg = <0x0 0xe1000000 0x0 0x02400000>;
label = "cont_splash_region";
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1000000>;
};
secure_display_memory: secure_display_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x8c00000>;
};
qcom: ramoops {
compatible = "ramoops";
reg = <0x0 0xa9000000 0x0 0x200000>;
pmsg-size = <0x200000>;
mem-type = <2>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
linux,cma-default;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
size = <0 0x2c00000>;
};
audio_cma_mem: audio_cma_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1C00000>;
};
splash_memory:splash_region {
reg = <0x0 0xe1000000 0x0 0x02300000>;
label = "cont_splash_region";
};
dfps_data_memory: dfps_data_memory {
reg = <0x0 0xe3300000 0x0 0x0100000>;
label = "dfps_data_memory";
};
memshare_mem: memshare_region {
compatible = "shared-dma-pool";
no-map;
/*
* Memory shared with modem needs to be outside of
* the CLADE address space, which begins at
* 0xE0000000 and spans 512 MB.
*/
alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
alignment = <0x0 0x100000>;
size = <0x0 0x800000>;
};
cnss_wlan_mem: cnss_wlan_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x1400000>;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
slim_aud: slim@3ac0000 {
cell-index = <1>;
compatible = "qcom,slim-ngd";
reg = <0x3ac0000 0x2c000>,
<0x3a84000 0x20000>;
reg-names = "slimbus_physical", "slimbus_bam_physical";
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
qcom,apps-ch-pipes = <0x0>;
qcom,ea-pc = <0x3e0>;
iommus = <&apps_smmu 0x1826 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
qcom,iommu-geometry = <0x40000000 0x10000000>;
qcom,iommu-dma = "fastmap";
status = "ok"
/* Slimbus Slave DT for QCA6490 */
btfmslim_codec: qca6490 {
compatible = "qcom,btfmslim_slave";
elemental-addr = [00 01 21 02 17 02];
qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
qcom,btfm-slim-ifd-elemental-addr = [00 00 21 02 17 02];
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17a00000 0x10000>, /* GICD */
<0x17a60000 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,yupik-pdc";
reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
<55 306 4>, <59 312 3>, <62 374 2>,
<64 434 2>, <66 438 3>, <69 86 1>,
<70 520 54>, <124 609 31>, <155 63 1>,
<156 716 12>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
wdog: qcom,wdt@17c10000 {
compatible = "qcom,msm-watchdog";
reg = <0x17c10000 0x1000>;
reg-names = "wdt-base";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
qcom_tzlog: tz-log@0x146aa720 {
compatible = "qcom,tz-log";
reg = <0x146aa720 0x3000>;
qcom,hyplog-enabled;
hyplog-address-offset = <0x410>;
hyplog-size-offset = <0x414>;
};
qcom_qseecom: qseecom@c1800000 {
compatible = "qcom,qseecom";
memory-region = <&qseecom_mem>;
qcom,hlos-num-ce-hw-instances = <1>;
qcom,hlos-ce-hw-instance = <0>;
qcom,qsee-ce-hw-instance = <0>;
qcom,disk-encrypt-pipe-pair = <2>;
qcom,support-fde;
qcom,no-clock-support;
qcom,fde-key-size;
qcom,appsbl-qseecom-support;
qcom,commonlib64-loaded-by-uefi;
qcom,qsee-reentrancy-support = <2>;
};
qcom_rng: qrng@10d3000 {
compatible = "qcom,msm-rng";
reg = <0x10d3000 0x1000>;
qcom,no-qrng-config;
interconnect-names = "data_path";
interconnects = <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_HWKM>;
clock-names = "km_clk_src";
clocks = <&rpmhcc RPMH_HWKM_CLK>;
};
qcom_cedev: qcedev@1de0000 {
compatible = "qcom,qcedev";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x24000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
qcom,bam-pipe-pair = <3>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,bam-ee = <0>;
qcom,smmu-s1-enable;
qcom,no-clock-support;
interconnect-names = "data_path";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
iommus = <&apps_smmu 0x04E6 0x0011>;
qcom,iommu-dma = "atomic";
qcom_cedev_ns_cb {
compatible = "qcom,qcedev,context-bank";
label = "ns_context";
iommus = <&apps_smmu 0x4F2 0>,
<&apps_smmu 0x4F8 0>,
<&apps_smmu 0x4F9 0>,
<&apps_smmu 0x4FF 0>;
};
qcom_cedev_s_cb {
compatible = "qcom,qcedev,context-bank";
label = "secure_context";
iommus = <&apps_smmu 0x4F3 0>,
<&apps_smmu 0x4FC 0>,
<&apps_smmu 0x4FD 0>,
<&apps_smmu 0x4FE 0>;
qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
qcom,secure-context-bank;
};
};
qcom_crypto: qcrypto@1de0000 {
compatible = "qcom,qcrypto";
reg = <0x1de0000 0x20000>,
<0x1dc4000 0x24000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
qcom,bam-pipe-pair = <2>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,bam-ee = <0>;
qcom,ce-hw-shared;
qcom,clk-mgmt-sus-res;
qcom,use-sw-aes-cbc-ecb-ctr-algo;
qcom,use-sw-aes-xts-algo;
qcom,use-sw-aes-ccm-algo;
qcom,use-sw-ahash-algo;
qcom,use-sw-aead-algo;
qcom,use-sw-hmac-algo;
qcom,smmu-s1-enable;
qcom,no-clock-support;
interconnect-names = "data_path";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
iommus = <&apps_smmu 0x04E4 0x0011>;
qcom,iommu-dma = "atomic";
};
qtee_shmbridge {
compatible = "qcom,tee-shared-memory-bridge";
};
qcom_smcinvoke {
compatible = "qcom,smcinvoke";
};
ipcc_mproc: qcom,ipcc@408000 {
compatible = "qcom,ipcc";
reg = <0x408000 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
memtimer: timer@17c20000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17c20000 0x1000>;
clock-frequency = <19200000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c27000 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
hyp_core_ctl: qcom,hyp-core-ctl {
compatible = "qcom,hyp-core-ctl";
status = "ok"
};
dcc: dcc_v2@117f000 {
compatible = "qcom,dcc-v2";
reg = <0x117f000 0x1000>,
<0x1112000 0x6000>;
qcom,transaction_timeout = <0>;
reg-names = "dcc-base", "dcc-ram-base";
dcc-ram-offset = <0x12000>;
link_list1 {
qcom,curr-link-list = <6>;
qcom,data-sink = "sram";
qcom,link-list = <DCC_READ 0x18000010 1 0>,
<DCC_READ 0x18000024 1 0>,
<DCC_READ 0x18000038 6 0>,
<DCC_READ 0x18010010 1 0>,
<DCC_READ 0x18010024 1 0>,
<DCC_READ 0x18010038 6 0>,
<DCC_READ 0x18020010 1 0>,
<DCC_READ 0x18020024 1 0>,
<DCC_READ 0x18020038 6 0>,
<DCC_READ 0x18030010 1 0>,
<DCC_READ 0x18030024 1 0>,
<DCC_READ 0x18030038 6 0>,
<DCC_READ 0x18040010 1 0>,
<DCC_READ 0x18040024 1 0>,
<DCC_READ 0x18040038 6 0>,
<DCC_READ 0x18050010 1 0>,
<DCC_READ 0x18050024 1 0>,
<DCC_READ 0x18050038 6 0>,
<DCC_READ 0x18060010 1 0>,
<DCC_READ 0x18060024 1 0>,
<DCC_READ 0x18060038 6 0>,
<DCC_READ 0x18070010 1 0>,
<DCC_READ 0x18070024 1 0>,
<DCC_READ 0x18070038 6 0>,
<DCC_READ 0x18080010 1 0>,
<DCC_READ 0x18080024 1 0>,
<DCC_READ 0x18080038 6 0>,
<DCC_READ 0x1808006c 5 0>,
<DCC_READ 0x18080084 1 0>,
<DCC_READ 0x180800f4 1 0>,
<DCC_READ 0x180800f8 1 0>,
<DCC_READ 0x180800fc 1 0>,
<DCC_READ 0x18080100 12 0>,
<DCC_READ 0x18080130 3 0>,
<DCC_READ 0x18080158 1 0>,
<DCC_READ 0x1808015c 1 0>,
<DCC_READ 0x18080160 1 0>,
<DCC_READ 0x18080164 1 0>,
<DCC_READ 0x18080168 1 0>,
<DCC_READ 0x18080170 1 0>,
<DCC_READ 0x18080174 1 0>,
<DCC_READ 0x18080188 1 0>,
<DCC_READ 0x1808018c 1 0>,
<DCC_READ 0x18080190 1 0>,
<DCC_READ 0x18080194 1 0>,
<DCC_READ 0x18080198 1 0>,
<DCC_READ 0x180801ac 1 0>,
<DCC_READ 0x180801b0 4 0>,
<DCC_READ 0x180801c0 1 0>,
<DCC_READ 0x180801c8 1 0>,
<DCC_READ 0x180801f0 1 0>,
<DCC_READ 0x18598020 1 0>,
<DCC_READ 0x1859001c 1 0>,
<DCC_READ 0x18590020 1 0>,
<DCC_READ 0x1859002c 1 0>,
<DCC_READ 0x18590064 1 0>,
<DCC_READ 0x18590068 1 0>,
<DCC_READ 0x1859006c 1 0>,
<DCC_READ 0x18590070 3 0>,
<DCC_READ 0x1859008c 1 0>,
<DCC_READ 0x185900dc 1 0>,
<DCC_READ 0x185900e8 1 0>,
<DCC_READ 0x185900ec 1 0>,
<DCC_READ 0x185900f0 1 0>,
<DCC_READ 0x18590300 1 0>,
<DCC_READ 0x1859030c 1 0>,
<DCC_READ 0x18590320 1 0>,
<DCC_READ 0x1859034c 1 0>,
<DCC_READ 0x185903bc 1 0>,
<DCC_READ 0x185903c0 1 0>,
<DCC_READ 0x1859101c 1 0>,
<DCC_READ 0x18591020 1 0>,
<DCC_READ 0x1859102c 1 0>,
<DCC_READ 0x18591064 1 0>,
<DCC_READ 0x18591068 1 0>,
<DCC_READ 0x1859106c 1 0>,
<DCC_READ 0x18591070 1 0>,
<DCC_READ 0x18591074 1 0>,
<DCC_READ 0x18591078 1 0>,
<DCC_READ 0x1859108c 1 0>,
<DCC_READ 0x185910dc 1 0>,
<DCC_READ 0x185910e8 1 0>,
<DCC_READ 0x185910ec 1 0>,
<DCC_READ 0x185910f0 1 0>,
<DCC_READ 0x18591300 1 0>,
<DCC_READ 0x1859130c 1 0>,
<DCC_READ 0x18591320 1 0>,
<DCC_READ 0x1859134c 1 0>,
<DCC_READ 0x185913bc 1 0>,
<DCC_READ 0x185913c0 1 0>,
<DCC_READ 0x1859201c 1 0>,
<DCC_READ 0x18592020 1 0>,
<DCC_READ 0x1859202c 1 0>,
<DCC_READ 0x18592064 1 0>,
<DCC_READ 0x18592068 1 0>,
<DCC_READ 0x1859206c 1 0>,
<DCC_READ 0x18592070 1 0>,
<DCC_READ 0x18592074 1 0>,
<DCC_READ 0x18592078 1 0>,
<DCC_READ 0x1859208c 1 0>,
<DCC_READ 0x185920dc 1 0>,
<DCC_READ 0x185920e8 1 0>,
<DCC_READ 0x185920ec 1 0>,
<DCC_READ 0x185920f0 1 0>,
<DCC_READ 0x18592300 1 0>,
<DCC_READ 0x1859230c 1 0>,
<DCC_READ 0x18592320 1 0>,
<DCC_READ 0x1859234c 1 0>,
<DCC_READ 0x185923bc 1 0>,
<DCC_READ 0x185923c0 1 0>,
<DCC_READ 0x1859301c 1 0>,
<DCC_READ 0x18593020 1 0>,
<DCC_READ 0x18593064 1 0>,
<DCC_READ 0x18593068 1 0>,
<DCC_READ 0x1859306c 1 0>,
<DCC_READ 0x18593070 1 0>,
<DCC_READ 0x18593074 1 0>,
<DCC_READ 0x18593078 1 0>,
<DCC_READ 0x1859308c 1 0>,
<DCC_READ 0x185930dc 1 0>,
<DCC_READ 0x185930e8 1 0>,
<DCC_READ 0x185930ec 1 0>,
<DCC_READ 0x185930f0 1 0>,
<DCC_READ 0x18593300 1 0>,
<DCC_READ 0x1859330c 1 0>,
<DCC_READ 0x18593320 1 0>,
<DCC_READ 0x1859302c 1 0>,
<DCC_READ 0x1859334c 1 0>,
<DCC_READ 0x185933bc 1 0>,
<DCC_READ 0x185933c0 1 0>,
<DCC_READ 0x18300000 1 0>,
<DCC_READ 0x1830000c 1 0>,
<DCC_READ 0x18300018 1 0>,
<DCC_READ 0x17c21000 2 0>,
<DCC_READ 0x18393a84 2 0>,
<DCC_READ 0x183a3a84 2 0>,
<DCC_READ 0x18280000 2 0>,
<DCC_READ 0x18282000 2 0>,
<DCC_READ 0x18284000 2 0>,
<DCC_READ 0x18286000 2 0>,
<DCC_READ 0x18300000 1 0>,
<DCC_READ 0x18200400 3 0>,
<DCC_READ 0x18200038 1 0>,
<DCC_READ 0x18200040 1 0>,
<DCC_READ 0x18200048 1 0>,
<DCC_READ 0x18220038 1 0>,
<DCC_READ 0x18220040 1 0>,
<DCC_READ 0x182200d0 1 0>,
<DCC_READ 0x18200030 1 0>,
<DCC_READ 0x18200010 1 0>,
<DCC_READ 0x610100 11 0>,
<DCC_READ 0x18000058 1 0>,
<DCC_READ 0x1800005c 1 0>,
<DCC_READ 0x18000060 1 0>,
<DCC_READ 0x18000064 1 0>,
<DCC_READ 0x1800006c 1 0>,
<DCC_READ 0x180000f0 2 0>,
<DCC_READ 0x18010058 1 0>,
<DCC_READ 0x1801005c 1 0>,
<DCC_READ 0x18010060 1 0>,
<DCC_READ 0x18010064 1 0>,
<DCC_READ 0x1801006c 1 0>,
<DCC_READ 0x180100f0 2 0>,
<DCC_READ 0x18020058 1 0>,
<DCC_READ 0x1802005c 1 0>,
<DCC_READ 0x18020060 1 0>,
<DCC_READ 0x18020064 1 0>,
<DCC_READ 0x1802006c 1 0>,
<DCC_READ 0x180200f0 2 0>,
<DCC_READ 0x18030058 1 0>,
<DCC_READ 0x1803005c 1 0>,
<DCC_READ 0x18030060 1 0>,
<DCC_READ 0x18030064 1 0>,
<DCC_READ 0x1803006c 1 0>,
<DCC_READ 0x180300f0 2 0>,
<DCC_READ 0x18040058 1 0>,
<DCC_READ 0x1804005c 1 0>,
<DCC_READ 0x18040060 1 0>,
<DCC_READ 0x18040064 1 0>,
<DCC_READ 0x1804006c 1 0>,
<DCC_READ 0x180400f0 2 0>,
<DCC_READ 0x18050058 1 0>,
<DCC_READ 0x1805005c 1 0>,
<DCC_READ 0x18050060 1 0>,
<DCC_READ 0x18050064 1 0>,
<DCC_READ 0x1805006c 1 0>,
<DCC_READ 0x180500f0 2 0>,
<DCC_READ 0x18060058 1 0>,
<DCC_READ 0x1806005c 1 0>,
<DCC_READ 0x18060060 1 0>,
<DCC_READ 0x18060064 1 0>,
<DCC_READ 0x1806006c 1 0>,
<DCC_READ 0x180600f0 2 0>,
<DCC_READ 0x18070058 1 0>,
<DCC_READ 0x1807005c 1 0>,
<DCC_READ 0x18070060 1 0>,
<DCC_READ 0x18070064 1 0>,
<DCC_READ 0x1807006c 1 0>,
<DCC_READ 0x180700f0 2 0>,
<DCC_READ 0x18101908 1 0>,
<DCC_READ 0x18101c18 1 0>,
<DCC_READ 0x18390810 1 0>,
<DCC_READ 0x18390c50 1 0>,
<DCC_READ 0x18390814 1 0>,
<DCC_READ 0x18390c54 1 0>,
<DCC_READ 0x18390818 1 0>,
<DCC_READ 0x18390c58 1 0>,
<DCC_READ 0x18393a84 2 0>,
<DCC_READ 0x18100908 1 0>,
<DCC_READ 0x18100c18 1 0>,
<DCC_READ 0x183a0810 1 0>,
<DCC_READ 0x183a0c50 1 0>,
<DCC_READ 0x183a0814 1 0>,
<DCC_READ 0x183a0c54 1 0>,
<DCC_READ 0x183a0818 1 0>,
<DCC_READ 0x183a0c58 1 0>,
<DCC_READ 0x183a3a84 2 0>,
<DCC_READ 0x18393500 1 0>,
<DCC_READ 0x18393580 1 0>,
<DCC_READ 0x183a3500 1 0>,
<DCC_READ 0x183a3580 1 0>,
<DCC_READ 0x18282000 4 0>,
<DCC_READ 0x18282028 1 0>,
<DCC_READ 0x18282038 1 0>,
<DCC_READ 0x18282080 5 0>,
<DCC_READ 0x18286000 4 0>,
<DCC_READ 0x18286028 1 0>,
<DCC_READ 0x18286038 1 0>,
<DCC_READ 0x18286080 5 0>,
<DCC_READ 0x0c201244 1 0>,
<DCC_READ 0x0c202244 1 0>,
<DCC_READ 0x18300000 1 0>,
<DCC_READ 0x1829208c 1 0>,
<DCC_READ 0x18292098 1 0>,
<DCC_READ 0x18292098 1 0>,
<DCC_READ 0x1829608c 1 0>,
<DCC_READ 0x18296098 1 0>,
<DCC_READ 0x18296098 1 0>,
<DCC_READ 0x00784184 1 0>,
<DCC_READ 0x9103008 1 0>,
<DCC_LOOP 0x5 0 0>,
<DCC_READ 0x9103010 1 0>,
<DCC_READ 0x9103014 1 0>,
<DCC_LOOP 0x1 0 0>,
<DCC_READ 0x9103408 1 0>,
<DCC_LOOP 0x5 0 0>,
<DCC_READ 0x9103410 1 0>,
<DCC_READ 0x9103414 1 0>,
<DCC_LOOP 0x1 0 0>,
<DCC_READ 0x9143008 1 0>,
<DCC_LOOP 0x5 0 0>,
<DCC_READ 0x9143010 1 0>,
<DCC_READ 0x9143014 1 0>,
<DCC_LOOP 0x1 0 0>,
<DCC_READ 0x9143408 1 0>,
<DCC_LOOP 0x5 0 0>,
<DCC_READ 0x9143410 1 0>,
<DCC_READ 0x9143414 1 0>,
<DCC_LOOP 0x1 0 0>,
<DCC_READ 0x91b0008 1 0>,
<DCC_LOOP 0x3 0 0>,
<DCC_READ 0x91b0010 1 0>,
<DCC_READ 0x91b0014 1 0>,
<DCC_LOOP 0x1 0 0>,
<DCC_READ 0x91b1008 1 0>,
<DCC_LOOP 0x10 0 0>,
<DCC_READ 0x91b1010 1 0>,
<DCC_READ 0x91b1014 1 0>,
<DCC_LOOP 0x1 0 0>,
<DCC_READ 0x9101808 1 0>,
<DCC_READ 0x910180c 1 0>,
<DCC_WRITE 0x9101828 0x00000001 1>,
<DCC_LOOP 0x41 0 0>,
<DCC_READ 0x9101810 1 0>,
<DCC_READ 0x9101814 1 0>,
<DCC_READ 0x9101818 1 0>,
<DCC_READ 0x910181c 1 0>,
<DCC_LOOP 0x1 0 0>,
<DCC_READ 0x9141808 1 0>,
<DCC_READ 0x914180c 1 0>,
<DCC_WRITE 0x9141828 0x00000001 1>,
<DCC_LOOP 0x41 0 0>,
<DCC_READ 0x9141810 1 0>,
<DCC_READ 0x9141814 1 0>,
<DCC_READ 0x9141818 1 0>,
<DCC_READ 0x914181c 1 0>,
<DCC_LOOP 0x1 0 0>,
<DCC_READ 0x91a8008 1 0>,
<DCC_READ 0x91a800c 1 0>,
<DCC_WRITE 0x91a8028 0x00000001 1>,
<DCC_LOOP 0x11 0 0>,
<DCC_READ 0x91a8010 1 0>,
<DCC_READ 0x91a8014 1 0>,
<DCC_READ 0x91a8018 1 0>,
<DCC_READ 0x91a801c 1 0>,
<DCC_LOOP 0x1 0 0>,
<DCC_READ 0x91a8808 1 0>,
<DCC_READ 0x91a880c 1 0>,
<DCC_WRITE 0x91a8828 0x00000001 1>,
<DCC_LOOP 0x11 0 0>,
<DCC_READ 0x91a8810 1 0>,
<DCC_READ 0x91a8814 1 0>,
<DCC_READ 0x91a8818 1 0>,
<DCC_READ 0x91a881c 1 0>,
<DCC_LOOP 0x1 0 0>,
<DCC_READ 0x9100000 1 0>,
<DCC_READ 0x9100008 1 0>,
<DCC_READ 0x910000c 1 0>,
<DCC_READ 0x9140000 1 0>,
<DCC_READ 0x9140008 1 0>,
<DCC_READ 0x914000c 1 0>,
<DCC_READ 0x9180000 1 0>,
<DCC_READ 0x9180008 1 0>,
<DCC_READ 0x918000c 1 0>,
<DCC_READ 0x9180404 1 0>,
<DCC_READ 0x9180408 1 0>,
<DCC_READ 0x918040c 1 0>,
<DCC_READ 0x9181010 1 0>,
<DCC_READ 0x9181020 8 0>,
<DCC_READ 0x91e1048 1 0>,
<DCC_READ 0x9121010 1 0>,
<DCC_READ 0x9122010 1 0>,
<DCC_READ 0x9123010 1 0>,
<DCC_READ 0x9125010 1 0>,
<DCC_READ 0x9161010 1 0>,
<DCC_READ 0x9162010 1 0>,
<DCC_READ 0x9163010 1 0>,
<DCC_READ 0x9165010 1 0>,
<DCC_READ 0x91cf010 1 0>,
<DCC_READ 0x91d0010 1 0>,
<DCC_READ 0x91d1010 1 0>,
<DCC_READ 0x91d2010 1 0>,
<DCC_READ 0x91d3010 1 0>,
<DCC_READ 0x91d4010 1 0>,
<DCC_READ 0x91d5010 1 0>,
<DCC_READ 0x91d6010 1 0>,
<DCC_READ 0x91d7010 1 0>,
<DCC_READ 0x9101408 1 0>,
<DCC_READ 0x9141410 1 0>,
<DCC_READ 0x9100810 1 0>,
<DCC_READ 0x9140810 1 0>,
<DCC_READ 0x9100820 1 0>,
<DCC_READ 0x9140820 1 0>,
<DCC_READ 0x9100828 1 0>,
<DCC_READ 0x910082c 1 0>,
<DCC_READ 0x9140828 1 0>,
<DCC_READ 0x914082c 1 0>,
<DCC_READ 0x0c222004 1 0>,
<DCC_READ 0x0c263014 1 0>,
<DCC_READ 0x0c2630e0 1 0>,
<DCC_READ 0x0c2630ec 1 0>,
<DCC_READ 0x0c2630a0 16 0>,
<DCC_READ 0x0c2630e8 1 0>,
<DCC_READ 0x0c26313c 1 0>,
<DCC_READ 0x0c223004 1 0>,
<DCC_READ 0x0c265014 1 0>,
<DCC_READ 0x0c2650e0 1 0>,
<DCC_READ 0x0c2650ec 1 0>,
<DCC_READ 0x0c2650a0 16 0>,
<DCC_READ 0x0c2650e8 1 0>,
<DCC_READ 0x0c26513c 1 0>,
<DCC_READ 0xc410000 1 0>,
<DCC_READ 0xc40af04 1 0>,
<DCC_READ 0xc40af10 1 0>,
<DCC_READ 0xc40a000 1 0>,
<DCC_READ 0xc40a018 1 0>,
<DCC_READ 0xc40a028 1 0>,
<DCC_READ 0xc40a02c 1 0>,
<DCC_READ 0xc40a100 1 0>,
<DCC_READ 0xc2a22fc 1 0>,
<DCC_READ 0xc2a2300 1 0>,
<DCC_READ 0xc2a2304 1 0>,
<DCC_READ 0xc440200 1 0>,
<DCC_READ 0xc440204 1 0>,
<DCC_READ 0xc442200 1 0>,
<DCC_READ 0xc442204 1 0>,
<DCC_READ 0xc442208 1 0>,
<DCC_READ 0xc44220c 1 0>,
<DCC_READ 0x3d9100c 1 0>,
<DCC_READ 0x3d91010 2 0>,
<DCC_READ 0x3d9106c 3 0>,
<DCC_READ 0x3d91004 1 0>,
<DCC_READ 0x3d91054 3 0>,
<DCC_READ 0x3d91060 2 0>,
<DCC_READ 0x3d91070 2 0>,
<DCC_READ 0x3d91080 3 0>,
<DCC_READ 0x3d91078 2 0>,
<DCC_READ 0x3d9108c 1 0>,
<DCC_READ 0x3d91090 1 0>,
<DCC_READ 0x3d91098 2 0>,
<DCC_READ 0x3d910a4 2 0>,
<DCC_READ 0x3d910f0 2 0>,
<DCC_READ 0x3d91100 1 0>,
<DCC_READ 0x3d91118 1 0>,
<DCC_READ 0x3d91164 2 0>,
<DCC_READ 0x3d91170 1 0>,
<DCC_READ 0x3d91178 1 0>,
<DCC_READ 0x3d91204 1 0>,
<DCC_READ 0x3d9120c 1 0>,
<DCC_READ 0x3d98024 1 0>,
<DCC_READ 0x3d9802c 1 0>,
<DCC_READ 0x3d98030 1 0>,
<DCC_READ 0x3d92000 2 0>,
<DCC_READ 0x3d93000 2 0>,
<DCC_READ 0x3d95000 2 0>,
<DCC_READ 0x3d96000 2 0>,
<DCC_READ 0x3d97000 2 0>,
<DCC_READ 0x119000 1 0>,
<DCC_READ 0x11903c 1 0>,
<DCC_READ 0x171004 2 0>,
<DCC_READ 0x17100c 1 0>,
<DCC_READ 0x171014 1 0>,
<DCC_READ 0x171018 1 0>,
<DCC_READ 0x171154 1 0>,
<DCC_READ 0x171158 1 0>,
<DCC_READ 0x17115c 1 0>,
<DCC_READ 0x17a04c 1 0>,
<DCC_READ 0x17b000 1 0>,
<DCC_READ 0x17b03c 1 0>,
<DCC_READ 0x17c000 1 0>,
<DCC_READ 0x17c03c 1 0>,
<DCC_READ 0x17d000 1 0>,
<DCC_READ 0x17d03c 1 0>,
<DCC_READ 0x17e000 1 0>,
<DCC_READ 0x17e03c 1 0>,
<DCC_READ 0x187000 1 0>,
<DCC_READ 0x18703c 1 0>,
<DCC_READ 0x3d91534 1 0>,
<DCC_READ 0x3d002b4 1 0>,
<DCC_READ 0x3d00410 2 0>,
<DCC_READ 0x3d00818 1 0>,
<DCC_READ 0x3d7e220 2 0>,
<DCC_READ 0x1680B00 1 0>,
<DCC_READ 0x1680008 1 0>,
<DCC_READ 0x1680010 1 0>,
<DCC_READ 0x1680020 8 0>,
<DCC_READ 0x1680248 1 0>,
<DCC_READ 0x1680b00 6 0>,
<DCC_READ 0x16e4008 1 0>,
<DCC_LOOP 4 0 0>,
<DCC_READ 0x16e4010 1 0>,
<DCC_READ 0x16e4014 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x1706208 1 0>,
<DCC_LOOP 4 0 0>,
<DCC_READ 0x1706210 1 0>,
<DCC_READ 0x1706214 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x16e0000 1 0>,
<DCC_READ 0x16e0010 1 0>,
<DCC_READ 0x16e0008 1 0>,
<DCC_READ 0x16e0020 8 0>,
<DCC_READ 0x16e5048 1 0>,
<DCC_READ 0x16e5248 1 0>,
<DCC_READ 0x16e5448 1 0>,
<DCC_READ 0x16e5100 5 0>,
<DCC_READ 0x16e5300 2 0>,
<DCC_READ 0x16e5500 2 0>,
<DCC_READ 0x1700000 1 0>,
<DCC_READ 0x1700008 1 0>,
<DCC_READ 0x1700010 1 0>,
<DCC_READ 0x1700020 8 0>,
<DCC_READ 0x170b100 5 0>,
<DCC_READ 0x170b048 1 0>,
<DCC_READ 0x100000 15 0>,
<DCC_READ 0x101000 15 0>,
<DCC_READ 0x176000 15 0>,
<DCC_READ 0x174000 15 0>,
<DCC_READ 0x113000 15 0>,
<DCC_READ 0x11a000 15 0>,
<DCC_READ 0x11c000 15 0>,
<DCC_READ 0x11c048 3 0>,
<DCC_READ 0x11e000 15 0>,
<DCC_READ 0x10401c 1 0>,
<DCC_READ 0x105074 1 0>,
<DCC_READ 0x183024 1 0>,
<DCC_READ 0x109050 1 0>,
<DCC_READ 0x123020 1 0>,
<DCC_READ 0x117024 1 0>,
<DCC_READ 0x117154 1 0>,
<DCC_READ 0x117284 1 0>,
<DCC_READ 0x1173b4 1 0>,
<DCC_READ 0x1174e4 1 0>,
<DCC_READ 0x117614 1 0>,
<DCC_READ 0x117744 1 0>,
<DCC_READ 0x117874 1 0>,
<DCC_READ 0x118024 1 0>,
<DCC_READ 0x118154 1 0>,
<DCC_READ 0x118284 1 0>,
<DCC_READ 0x1183b4 1 0>,
<DCC_READ 0x1184e4 1 0>,
<DCC_READ 0x118614 1 0>,
<DCC_READ 0x118744 1 0>,
<DCC_READ 0x118874 1 0>,
<DCC_READ 0x129020 1 0>,
<DCC_READ 0x11d020 1 0>,
<DCC_READ 0x134024 1 0>,
<DCC_READ 0x141024 1 0>,
<DCC_READ 0x14415c 1 0>,
<DCC_READ 0x14504c 1 0>,
<DCC_READ 0x18903c 1 0>,
<DCC_READ 0x151000 1 0>,
<DCC_READ 0x151008 1 0>,
<DCC_READ 0x151010 1 0>,
<DCC_READ 0x152000 1 0>,
<DCC_READ 0x152008 1 0>,
<DCC_READ 0x152010 1 0>,
<DCC_READ 0x153020 1 0>,
<DCC_READ 0x153028 1 0>,
<DCC_READ 0x153030 1 0>,
<DCC_READ 0x155000 1 0>,
<DCC_READ 0x155008 1 0>,
<DCC_READ 0x155010 1 0>,
<DCC_READ 0x15b000 1 0>,
<DCC_READ 0x15b008 1 0>,
<DCC_READ 0x15b010 1 0>,
<DCC_READ 0x157000 1 0>,
<DCC_READ 0x157008 1 0>,
<DCC_READ 0x157010 1 0>,
<DCC_READ 0x135020 1 0>,
<DCC_READ 0x135028 1 0>,
<DCC_READ 0x135030 1 0>,
<DCC_READ 0x156000 1 0>,
<DCC_READ 0x156008 1 0>,
<DCC_READ 0x156010 1 0>,
<DCC_READ 0x15a000 1 0>,
<DCC_READ 0x15a008 1 0>,
<DCC_READ 0x15a010 1 0>,
<DCC_READ 0x190004 1 0>,
<DCC_READ 0x109008 1 0>,
<DCC_READ 0x190010 1 0>,
<DCC_READ 0x190020 1 0>,
<DCC_READ 0x190028 1 0>,
<DCC_READ 0x109010 1 0>,
<DCC_READ 0x109018 1 0>,
<DCC_READ 0x109018 1 0>,
<DCC_READ 0x109020 1 0>,
<DCC_READ 0x18d080 1 0>,
<DCC_READ 0x145014 1 0>,
<DCC_READ 0x14501c 1 0>,
<DCC_READ 0x183004 1 0>,
<DCC_READ 0x183008 1 0>,
<DCC_READ 0x183140 1 0>,
<DCC_READ 0x171158 2 0>,
<DCC_READ 0x109004 3 0>,
<DCC_READ 0x109160 1 0>,
<DCC_READ 0x109468 1 0>,
<DCC_READ 0x10f004 3 0>,
<DCC_READ 0x145000 3 0>,
<DCC_READ 0x16b004 3 0>,
<DCC_READ 0x18d004 3 0>,
<DCC_READ 0x177004 3 0>,
<DCC_READ 0x189004 3 0>,
<DCC_READ 0x153000 9 0>,
<DCC_READ 0x135000 9 0>,
<DCC_READ 0x106100 1 0>,
<DCC_READ 0x147004 1 0>,
<DCC_READ 0x17b000 1 0>,
<DCC_READ 0x17b004 1 0>,
<DCC_READ 0x17b008 1 0>,
<DCC_READ 0x17b00c 1 0>,
<DCC_READ 0x17b010 1 0>,
<DCC_READ 0x17b014 1 0>,
<DCC_READ 0x17b018 1 0>,
<DCC_READ 0x17b01c 1 0>,
<DCC_READ 0x17b020 1 0>,
<DCC_READ 0x17b024 1 0>,
<DCC_READ 0x17b028 1 0>,
<DCC_READ 0x17b02c 1 0>,
<DCC_READ 0x17b03c 1 0>,
<DCC_READ 0x17b040 1 0>,
<DCC_READ 0x17b044 1 0>,
<DCC_READ 0x17b048 1 0>,
<DCC_READ 0x17b04c 1 0>,
<DCC_READ 0x17b050 1 0>,
<DCC_READ 0x17b054 1 0>,
<DCC_READ 0x17b058 1 0>,
<DCC_READ 0x17b05c 1 0>,
<DCC_READ 0x17b060 1 0>,
<DCC_READ 0x17b064 1 0>,
<DCC_READ 0x17b068 1 0>,
<DCC_READ 0x17c000 1 0>,
<DCC_READ 0x17c004 1 0>,
<DCC_READ 0x17c008 1 0>,
<DCC_READ 0x17c00c 1 0>,
<DCC_READ 0x17c010 1 0>,
<DCC_READ 0x17c014 1 0>,
<DCC_READ 0x17c018 1 0>,
<DCC_READ 0x17c01c 1 0>,
<DCC_READ 0x17c020 1 0>,
<DCC_READ 0x17c024 1 0>,
<DCC_READ 0x17c028 1 0>,
<DCC_READ 0x17c02c 1 0>,
<DCC_READ 0x17c03c 1 0>,
<DCC_READ 0x17c040 1 0>,
<DCC_READ 0x17c044 1 0>,
<DCC_READ 0x17c048 1 0>,
<DCC_READ 0x17c04c 1 0>,
<DCC_READ 0x17c050 1 0>,
<DCC_READ 0x17c054 1 0>,
<DCC_READ 0x17c058 1 0>,
<DCC_READ 0x17c05c 1 0>,
<DCC_READ 0x17c060 1 0>,
<DCC_READ 0x17c064 1 0>,
<DCC_READ 0x17c068 1 0>,
<DCC_READ 0x153124 1 0>,
<DCC_READ 0x156124 1 0>,
<DCC_READ 0x1453a4 1 0>,
<DCC_READ 0x182884 1 0>,
<DCC_READ 0x145384 1 0>,
<DCC_READ 0xc2a0000 15 0>,
<DCC_READ 0xc2a1000 15 0>,
<DCC_READ 0x17101c 1 0>,
<DCC_READ 0x171020 1 0>,
<DCC_READ 0x14401c 1 0>,
<DCC_READ 0x144020 1 0>,
<DCC_READ 0x183010 1 0>,
<DCC_READ 0x183014 1 0>,
<DCC_READ 0x18a160 1 0>,
<DCC_READ 0x18a164 1 0>,
<DCC_READ 0x18a004 1 0>,
<DCC_READ 0x18a01c 1 0>,
<DCC_READ 0x18a020 1 0>,
<DCC_READ 0x18a024 1 0>,
<DCC_READ 0x19d004 1 0>,
<DCC_READ 0x19d008 1 0>,
<DCC_READ 0x196100 1 0>,
<DCC_READ 0x10003c 1 0>,
<DCC_READ 0x10103c 1 0>,
<DCC_READ 0x10203c 1 0>,
<DCC_READ 0x10303c 1 0>,
<DCC_READ 0x11303c 1 0>,
<DCC_READ 0x11a03c 1 0>,
<DCC_READ 0x11c03c 1 0>,
<DCC_READ 0x17403c 1 0>,
<DCC_READ 0x17603c 1 0>,
<DCC_READ 0x11e03c 1 0>,
<DCC_READ 0xbbf0004 12 0>,
<DCC_READ 0xbbf0800 12 0>,
<DCC_READ 0xbbf0004 12 0>,
<DCC_READ 0xbbf0800 12 0>;
};
link_list2 {
qcom,curr-link-list = <4>;
qcom,data-sink = "sram";
qcom,link-list = <DCC_READ 0x01510008 1 0>,
<DCC_LOOP 9 0 0>,
<DCC_READ 0x151d010 1 0>,
<DCC_READ 0x151d014 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_LOOP 9 0 0>,
<DCC_READ 0x1506010 1 0>,
<DCC_READ 0x1506014 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x151d208 1 0>,
<DCC_READ 0x1507008 1 0>,
<DCC_LOOP 2 0 0>,
<DCC_READ 0x151d210 1 0>,
<DCC_READ 0x151d214 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_LOOP 2 0 0>,
<DCC_READ 0x1507010 1 0>,
<DCC_READ 0x1507014 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x151d308 1 0>,
<DCC_READ 0x1509008 1 0>,
<DCC_LOOP 3 0 0>,
<DCC_READ 0x1509010 1 0>,
<DCC_READ 0x1509014 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_LOOP 3 0 0>,
<DCC_READ 0x151d310 1 0>,
<DCC_READ 0x151d314 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x01514008 1 0>,
<DCC_LOOP 3 0 0>,
<DCC_READ 0x01514010 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x1500000 1 0>,
<DCC_READ 0x1510000 1 0>,
<DCC_READ 0x1500010 1 0>,
<DCC_READ 0x1510010 1 0>,
<DCC_READ 0x1500020 8 0>,
<DCC_READ 0x1510020 8 0>,
<DCC_READ 0x1511048 1 0>,
<DCC_READ 0x1501048 2 0>,
<DCC_READ 0x1501058 1 0>,
<DCC_READ 0x1501248 1 0>,
<DCC_READ 0x1511248 1 0>,
<DCC_READ 0x1501248 1 0>,
<DCC_READ 0x1511b00 1 0>,
<DCC_READ 0x151e100 1 0>,
<DCC_READ 0x150b100 1 0>,
<DCC_READ 0xec80004 1 0>,
<DCC_READ 0xec80058 1 0>,
<DCC_READ 0xec80060 8 0>,
<DCC_READ 0xec800a0 8 0>,
<DCC_READ 0xec800c0 16 0>,
<DCC_READ 0xec80100 16 0>,
<DCC_READ 0x634008 1 0>,
<DCC_READ 0x634f00 8 0>,
<DCC_READ 0x635560 1 0>,
<DCC_READ 0x635570 1 0>,
<DCC_READ 0x635580 1 0>,
<DCC_READ 0x635590 1 0>,
<DCC_READ 0x6355a0 4 0>,
<DCC_READ 0x635600 1 0>,
<DCC_READ 0x635610 1 0>,
<DCC_READ 0x636008 1 0>,
<DCC_READ 0x636f00 8 0>,
<DCC_READ 0x637560 1 0>,
<DCC_READ 0x637570 1 0>,
<DCC_READ 0x637580 1 0>,
<DCC_READ 0x637590 1 0>,
<DCC_READ 0x6375a0 4 0>,
<DCC_READ 0x637600 1 0>,
<DCC_READ 0x637610 1 0>,
<DCC_READ 0x18370220 2 0>,
<DCC_READ 0x183702a0 2 0>,
<DCC_READ 0x183704a0 12 0>,
<DCC_READ 0x18370520 1 0>,
<DCC_READ 0x18370588 1 0>,
<DCC_READ 0x18370d10 12 0>,
<DCC_READ 0x18370f90 10 0>,
<DCC_READ 0x18371010 10 0>,
<DCC_READ 0x18371a10 8 0>,
<DCC_READ 0x183784a0 12 0>,
<DCC_READ 0x18378520 1 0>,
<DCC_READ 0x18378588 1 0>,
<DCC_READ 0x18378d10 8 0>,
<DCC_READ 0x18378f90 6 0>,
<DCC_READ 0x18379010 6 0>,
<DCC_READ 0x18379a10 4 0>,
<DCC_READ 0xa310220 3 0>,
<DCC_READ 0xa3102a0 3 0>,
<DCC_READ 0xa3104a0 6 0>,
<DCC_READ 0xa310520 1 0>,
<DCC_READ 0xa310588 1 0>,
<DCC_READ 0xa310d10 8 0>,
<DCC_READ 0xa310f90 6 0>,
<DCC_READ 0xa311010 6 0>,
<DCC_READ 0xa311a10 3 0>,
<DCC_READ 0x17a00104 29 0>,
<DCC_READ 0x17a00204 29 0>,
<DCC_READ 0x01741008 1 0>,
<DCC_LOOP 9 0 0>,
<DCC_READ 0x01741010 1 0>,
<DCC_READ 0x01741014 1 0>,
<DCC_LOOP 1 0 0>,
<DCC_READ 0x1740000 1 0>,
<DCC_READ 0x1740008 1 0>,
<DCC_READ 0x1740010 1 0>,
<DCC_READ 0x1740020 8 0>,
<DCC_READ 0x174b048 1 0>,
<DCC_READ 0x174b100 8 0>,
<DCC_READ 0x90e0000 1 0>,
<DCC_READ 0x90e0008 1 0>,
<DCC_READ 0x90e0010 1 0>,
<DCC_READ 0x90e0020 8 0>,
<DCC_READ 0x90e0248 1 0>,
<DCC_READ 0x90e3100 1 0>,
<DCC_READ 0x90e4100 7 0>,
<DCC_READ 0x1750010 1 0>,
<DCC_READ 0x1750190 1 0>,
<DCC_READ 0x1751010 1 0>,
<DCC_READ 0x1752010 1 0>,
<DCC_READ 0x1754010 1 0>,
<DCC_READ 0x1755010 1 0>,
<DCC_READ 0x1756010 1 0>,
<DCC_READ 0x1758010 1 0>,
<DCC_READ 0x1758090 1 0>,
<DCC_READ 0x1759010 1 0>,
<DCC_READ 0x175a010 1 0>,
<DCC_READ 0x175c010 1 0>,
<DCC_READ 0x175d010 1 0>,
<DCC_READ 0x175e010 1 0>,
<DCC_READ 0x0b201020 2 0>,
<DCC_READ 0x0b200010 4 0>,
<DCC_READ 0x0b220010 4 0>,
<DCC_READ 0x0b200900 4 0>,
<DCC_READ 0x0b220900 4 0>,
<DCC_READ 0x0b201030 1 0>,
<DCC_READ 0x0b201204 1 0>,
<DCC_READ 0x0b201218 1 0>,
<DCC_READ 0x0b20122c 1 0>,
<DCC_READ 0x0b201240 1 0>,
<DCC_READ 0x0b201254 1 0>,
<DCC_READ 0x0b201208 1 0>,
<DCC_READ 0x0b20121c 1 0>,
<DCC_READ 0x0b201230 1 0>,
<DCC_READ 0x0b201244 1 0>,
<DCC_READ 0x0b201258 1 0>,
<DCC_READ 0x0b204510 1 0>,
<DCC_READ 0x0b204514 1 0>,
<DCC_READ 0x0b204520 1 0>,
<DCC_READ 0x0b211024 1 0>,
<DCC_READ 0x0b221024 1 0>,
<DCC_READ 0x0b231024 1 0>,
<DCC_READ 0x18220010 1 0>,
<DCC_READ 0x18220030 1 0>,
<DCC_READ 0x182200d0 1 0>,
<DCC_READ 0x18220408 1 0>,
<DCC_READ 0x18230408 1 0>,
<DCC_READ 0x17e00434 1 0>,
<DCC_READ 0x17e0043c 2 0>,
<DCC_READ 0x17c00038 2 0>,
<DCC_READ 0x17c00438 1 0>,
<DCC_READ 0x17e0041c 1 0>,
<DCC_READ 0x17e00420 1 0>,
<DCC_READ 0x17e00404 1 0>,
<DCC_READ 0xc220000 2 0>,
<DCC_READ 0xc230000 6 0>,
<DCC_READ 0xc260008 1 0>,
<DCC_READ 0x18598014 1 0>,
<DCC_READ 0x4d8634 1 0>,
<DCC_READ 0x4d8834 1 0>,
<DCC_READ 0x418620 1 0>,
<DCC_READ 0x418820 1 0>,
<DCC_READ 0x9084208 1 0>,
<DCC_READ 0x9084204 1 0>,
<DCC_READ 0x9084108 1 0>,
<DCC_READ 0x90841c0 1 0>,
<DCC_READ 0x10c034 1 0>,
<DCC_READ 0x10c038 1 0>,
<DCC_READ 0x144018 1 0>,
<DCC_WRITE 0x90841c0 0x1 0>,
<DCC_WRITE 0x10c034 0x1 0>,
<DCC_WRITE 0x10c038 0x1 0>,
<DCC_WRITE 0x144018 0x1 0>,
<DCC_READ 0x9050078 1 0>,
<DCC_READ 0x9050110 8 0>,
<DCC_READ 0x9080058 2 0>,
<DCC_READ 0x90800c8 1 0>,
<DCC_READ 0x90800d4 1 0>,
<DCC_READ 0x90800e0 1 0>,
<DCC_READ 0x90800fc 1 0>,
<DCC_READ 0x9084030 1 0>,
<DCC_READ 0x9084038 2 0>,
<DCC_READ 0x90840e4 1 0>,
<DCC_READ 0x90840f4 1 0>,
<DCC_READ 0x9084104 2 0>,
<DCC_READ 0x9084198 1 0>,
<DCC_READ 0x9084804 1 0>,
<DCC_READ 0x908480c 1 0>,
<DCC_READ 0x9084844 1 0>,
<DCC_READ 0x9084850 2 0>,
<DCC_READ 0x9084860 3 0>,
<DCC_READ 0x9084888 1 0>,
<DCC_READ 0x908488c 1 0>,
<DCC_READ 0x908409c 1 0>,
<DCC_READ 0x90840a0 1 0>,
<DCC_READ 0x908426c 1 0>,
<DCC_READ 0x908439c 1 0>,
<DCC_READ 0x9085124 1 0>,
<DCC_READ 0x9085134 1 0>,
<DCC_READ 0x9085138 1 0>,
<DCC_READ 0x9084840 1 0>,
<DCC_READ 0x9084834 1 0>,
<DCC_READ 0x9085124 1 0>,
<DCC_READ 0x90ba280 1 0>,
<DCC_READ 0x90ba288 7 0>,
<DCC_READ 0x9258610 4 0>,
<DCC_READ 0x92d8610 4 0>,
<DCC_READ 0x9220344 8 0>,
<DCC_READ 0x9220370 6 0>,
<DCC_READ 0x9220480 1 0>,
<DCC_READ 0x9222400 1 0>,
<DCC_READ 0x922240c 1 0>,
<DCC_READ 0x9223214 2 0>,
<DCC_READ 0x9223220 3 0>,
<DCC_READ 0x9223308 1 0>,
<DCC_READ 0x9223318 1 0>,
<DCC_READ 0x9232100 1 0>,
<DCC_READ 0x9236040 6 0>,
<DCC_READ 0x92360b0 1 0>,
<DCC_READ 0x923a004 4 0>,
<DCC_READ 0x923e030 2 0>,
<DCC_READ 0x9241000 1 0>,
<DCC_READ 0x9242028 1 0>,
<DCC_READ 0x9242044 3 0>,
<DCC_READ 0x9242070 1 0>,
<DCC_READ 0x9248030 1 0>,
<DCC_READ 0x9248048 8 0>,
<DCC_READ 0x9238030 1 0>,
<DCC_READ 0x9238060 1 0>,
<DCC_READ 0x9238064 1 0>,
<DCC_READ 0x9238074 1 0>,
<DCC_READ 0x9238088 1 0>,
<DCC_READ 0x92380a0 1 0>,
<DCC_READ 0x92380b0 1 0>,
<DCC_READ 0x92a0344 8 0>,
<DCC_READ 0x92a0370 6 0>,
<DCC_READ 0x92a0480 1 0>,
<DCC_READ 0x92a2400 1 0>,
<DCC_READ 0x92a240c 1 0>,
<DCC_READ 0x92a3214 2 0>,
<DCC_READ 0x92a3220 3 0>,
<DCC_READ 0x92a3308 1 0>,
<DCC_READ 0x92a3318 1 0>,
<DCC_READ 0x92b2100 1 0>,
<DCC_READ 0x92b6040 6 0>,
<DCC_READ 0x92b60b0 1 0>,
<DCC_READ 0x92ba004 4 0>,
<DCC_READ 0x92be030 2 0>,
<DCC_READ 0x92c1000 1 0>,
<DCC_READ 0x92c2028 1 0>,
<DCC_READ 0x92c2044 3 0>,
<DCC_READ 0x92c2070 1 0>,
<DCC_READ 0x92c8030 1 0>,
<DCC_READ 0x92c8048 8 0>,
<DCC_READ 0x92b8030 1 0>,
<DCC_READ 0x92b8060 1 0>,
<DCC_READ 0x92b8064 1 0>,
<DCC_READ 0x92b8074 1 0>,
<DCC_READ 0x92b8088 1 0>,
<DCC_READ 0x92b80a0 1 0>,
<DCC_READ 0x92b80b0 1 0>,
<DCC_READ 0x92c8064 1 0>,
<DCC_READ 0x9270080 1 0>,
<DCC_READ 0x9270310 1 0>,
<DCC_READ 0x9270400 1 0>,
<DCC_READ 0x9270410 6 0>,
<DCC_READ 0x9270430 1 0>,
<DCC_READ 0x9270440 1 0>,
<DCC_READ 0x9270448 1 0>,
<DCC_READ 0x92704a0 1 0>,
<DCC_READ 0x92704b0 1 0>,
<DCC_READ 0x92704b8 2 0>,
<DCC_READ 0x92704d0 2 0>,
<DCC_READ 0x9271400 1 0>,
<DCC_READ 0x9271408 1 0>,
<DCC_READ 0x927341c 1 0>,
<DCC_READ 0x9273420 1 0>,
<DCC_READ 0x92753b0 1 0>,
<DCC_READ 0x9275804 1 0>,
<DCC_READ 0x9275c18 2 0>,
<DCC_READ 0x9275c2c 1 0>,
<DCC_READ 0x9275c38 1 0>,
<DCC_READ 0x9276418 2 0>,
<DCC_READ 0x9279100 1 0>,
<DCC_READ 0x9279110 1 0>,
<DCC_READ 0x9279120 1 0>,
<DCC_READ 0x9279180 2 0>,
<DCC_READ 0x92f0080 1 0>,
<DCC_READ 0x92f0310 1 0>,
<DCC_READ 0x92f0400 1 0>,
<DCC_READ 0x92f0410 6 0>,
<DCC_READ 0x92f0430 1 0>,
<DCC_READ 0x92f0440 1 0>,
<DCC_READ 0x92f0448 1 0>,
<DCC_READ 0x92f04a0 1 0>,
<DCC_READ 0x92f04b0 1 0>,
<DCC_READ 0x92f04b8 2 0>,
<DCC_READ 0x92f04d0 2 0>,
<DCC_READ 0x92f1400 1 0>,
<DCC_READ 0x92f1408 1 0>,
<DCC_READ 0x92f341c 1 0>,
<DCC_READ 0x92f3420 1 0>,
<DCC_READ 0x92f53b0 1 0>,
<DCC_READ 0x92f5804 1 0>,
<DCC_READ 0x92f5c18 2 0>,
<DCC_READ 0x92f5c2c 1 0>,
<DCC_READ 0x92f5c38 1 0>,
<DCC_READ 0x92f6418 2 0>,
<DCC_READ 0x92f9100 1 0>,
<DCC_READ 0x92f9110 1 0>,
<DCC_READ 0x92f9120 1 0>,
<DCC_READ 0x92f9180 2 0>,
<DCC_READ 0x9260080 1 0>,
<DCC_READ 0x9260400 1 0>,
<DCC_READ 0x9260410 3 0>,
<DCC_READ 0x9260420 2 0>,
<DCC_READ 0x9260430 1 0>,
<DCC_READ 0x9260440 1 0>,
<DCC_READ 0x9260448 1 0>,
<DCC_READ 0x92604a0 1 0>,
<DCC_READ 0x92604b0 1 0>,
<DCC_READ 0x92604b8 2 0>,
<DCC_READ 0x92604d0 2 0>,
<DCC_READ 0x9261400 1 0>,
<DCC_READ 0x9263410 1 0>,
<DCC_READ 0x92653b0 1 0>,
<DCC_READ 0x9265804 1 0>,
<DCC_READ 0x9265b1c 1 0>,
<DCC_READ 0x9265b2c 1 0>,
<DCC_READ 0x9265b38 1 0>,
<DCC_READ 0x9269100 1 0>,
<DCC_READ 0x9269108 1 0>,
<DCC_READ 0x9269110 1 0>,
<DCC_READ 0x9269118 1 0>,
<DCC_READ 0x9269120 1 0>,
<DCC_READ 0x9269180 2 0>,
<DCC_READ 0x92e0080 1 0>,
<DCC_READ 0x92e0400 1 0>,
<DCC_READ 0x92e0410 3 0>,
<DCC_READ 0x92e0420 2 0>,
<DCC_READ 0x92e0430 1 0>,
<DCC_READ 0x92e0440 1 0>,
<DCC_READ 0x92e0448 1 0>,
<DCC_READ 0x92e04a0 1 0>,
<DCC_READ 0x92e04b0 1 0>,
<DCC_READ 0x92e04b8 2 0>,
<DCC_READ 0x92e04d0 2 0>,
<DCC_READ 0x92e1400 1 0>,
<DCC_READ 0x92e3410 1 0>,
<DCC_READ 0x92e53b0 1 0>,
<DCC_READ 0x92e5804 1 0>,
<DCC_READ 0x92e5b1c 1 0>,
<DCC_READ 0x92e5b2c 1 0>,
<DCC_READ 0x92e5b38 1 0>,
<DCC_READ 0x92e9100 1 0>,
<DCC_READ 0x92e9108 1 0>,
<DCC_READ 0x92e9110 1 0>,
<DCC_READ 0x92e9118 1 0>,
<DCC_READ 0x92e9120 1 0>,
<DCC_READ 0x92e9180 2 0>,
<DCC_READ 0x96b0868 1 0>,
<DCC_READ 0x96b0870 1 0>,
<DCC_READ 0x96b1004 1 0>,
<DCC_READ 0x96b100c 1 0>,
<DCC_READ 0x96b1014 1 0>,
<DCC_READ 0x96b1204 1 0>,
<DCC_READ 0x96b120c 1 0>,
<DCC_READ 0x96b1214 1 0>,
<DCC_READ 0x96b1504 1 0>,
<DCC_READ 0x96b150c 1 0>,
<DCC_READ 0x96b1514 1 0>,
<DCC_READ 0x96b1604 1 0>,
<DCC_READ 0x96b8100 1 0>,
<DCC_READ 0x96b813c 1 0>,
<DCC_READ 0x96b8500 1 0>,
<DCC_READ 0x96b853c 1 0>,
<DCC_READ 0x96b8a04 1 0>,
<DCC_READ 0x96b8a18 1 0>,
<DCC_READ 0x96b8ea8 1 0>,
<DCC_READ 0x96b9044 1 0>,
<DCC_READ 0x96b904c 1 0>,
<DCC_READ 0x96b9054 1 0>,
<DCC_READ 0x96b905c 1 0>,
<DCC_READ 0x96b910c 2 0>,
<DCC_READ 0x96b9204 1 0>,
<DCC_READ 0x96b920c 1 0>,
<DCC_READ 0x96b9238 1 0>,
<DCC_READ 0x96b9240 1 0>,
<DCC_READ 0x96b926c 1 0>,
<DCC_READ 0x96b9394 1 0>,
<DCC_READ 0x96b939c 1 0>,
<DCC_READ 0x96b9704 1 0>,
<DCC_READ 0x96b970c 1 0>,
<DCC_READ 0x96f0868 1 0>,
<DCC_READ 0x96f0870 1 0>,
<DCC_READ 0x96f1004 1 0>,
<DCC_READ 0x96f100c 1 0>,
<DCC_READ 0x96f1014 1 0>,
<DCC_READ 0x96f1204 1 0>,
<DCC_READ 0x96f120c 1 0>,
<DCC_READ 0x96f1214 1 0>,
<DCC_READ 0x96f1504 1 0>,
<DCC_READ 0x96f150c 1 0>,
<DCC_READ 0x96f1514 1 0>,
<DCC_READ 0x96f1604 1 0>,
<DCC_READ 0x96f8100 1 0>,
<DCC_READ 0x96f813c 1 0>,
<DCC_READ 0x96f8500 1 0>,
<DCC_READ 0x96f853c 1 0>,
<DCC_READ 0x96f8a04 1 0>,
<DCC_READ 0x96f8a18 1 0>,
<DCC_READ 0x96f8ea8 1 0>,
<DCC_READ 0x96f9044 1 0>,
<DCC_READ 0x96f904c 1 0>,
<DCC_READ 0x96f9054 1 0>,
<DCC_READ 0x96f905c 1 0>,
<DCC_READ 0x96f910c 2 0>,
<DCC_READ 0x96f9204 1 0>,
<DCC_READ 0x96f920c 1 0>,
<DCC_READ 0x96f9238 1 0>,
<DCC_READ 0x96f9240 1 0>,
<DCC_READ 0x96f926c 1 0>,
<DCC_READ 0x96f9394 1 0>,
<DCC_READ 0x96f939c 1 0>,
<DCC_READ 0x96f9704 1 0>,
<DCC_READ 0x96f970c 1 0>,
<DCC_READ 0x9130100 3 0>,
<DCC_READ 0x9170100 3 0>,
<DCC_READ 0x91dd100 4 0>,
<DCC_READ 0x91df100 1 0>,
<DCC_READ 0x610110 5 0>,
<DCC_READ 0x9230010 1 0>,
<DCC_READ 0x9230020 1 0>,
<DCC_READ 0x9230030 1 0>,
<DCC_READ 0x9230040 1 0>,
<DCC_READ 0x92b0010 1 0>,
<DCC_READ 0x92b0020 1 0>,
<DCC_READ 0x92b0030 1 0>,
<DCC_READ 0x92b0040 1 0>,
<DCC_READ 0x9232050 1 0>,
<DCC_READ 0x923605c 2 0>,
<DCC_READ 0x92360a0 1 0>,
<DCC_READ 0x923a018 2 0>,
<DCC_READ 0x92b2050 1 0>,
<DCC_READ 0x92b605c 2 0>,
<DCC_READ 0x92b60a0 1 0>,
<DCC_READ 0x92ba018 2 0>,
<DCC_READ 0x9222404 2 0>,
<DCC_READ 0x9222410 1 0>,
<DCC_READ 0x9238004 1 0>,
<DCC_READ 0x9238014 1 0>,
<DCC_READ 0x923805c 1 0>,
<DCC_READ 0x923a014 1 0>,
<DCC_READ 0x92a2404 2 0>,
<DCC_READ 0x92a2410 1 0>,
<DCC_READ 0x92b8004 1 0>,
<DCC_READ 0x92b8014 1 0>,
<DCC_READ 0x92b805c 1 0>,
<DCC_READ 0x92ba014 1 0>,
<DCC_WRITE 0x06e0a00c 0x00600007 1>,
<DCC_WRITE 0x06e0a01c 0x00136800 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136810 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136820 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136830 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136840 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136850 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136860 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x00136870 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003e9a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003c0a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003d1a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003d2a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003d5a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003d6a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003e8a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003eea0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003b1a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003b2a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003b5a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003b6a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003c2a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003c5a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a01c 0x0003c6a0 1>,
<DCC_WRITE 0x06e0a01c 0x001368a0 1>,
<DCC_READ 0x06e0a014 1 1>,
<DCC_WRITE 0x06e0a014 0x0002000c 1>,
<DCC_WRITE 0x06e0a01c 0x000368b0 1>,
<DCC_WRITE 0x06e0a01c 0x00000ba8 1>,
<DCC_WRITE 0x06e0a01c 0x0013b6a0 1>,
<DCC_WRITE 0x06e0a01c 0x00f1e000 1>,
<DCC_WRITE 0x06e0a008 0x00000007 1>,
<DCC_READ 0x09067e00 124 0>,
<DCC_READ 0x905000c 1 0>,
<DCC_READ 0x9050948 1 0>,
<DCC_READ 0x9050078 1 0>,
<DCC_READ 0x9050008 1 0>;
};
link_list3 {
qcom,curr-link-list = <3>;
qcom,data-sink = "sram";
qcom,link-list = <DCC_READ 0xb2c4520 1 0>,
<DCC_READ 0xb2c1020 2 0>,
<DCC_READ 0xb2c1030 1 0>,
<DCC_READ 0xb2c1200 1 0>,
<DCC_READ 0xb2c1214 1 0>,
<DCC_READ 0xb2c1228 1 0>,
<DCC_READ 0xb2c123c 1 0>,
<DCC_READ 0xb2c1250 1 0>,
<DCC_READ 0xb2c1204 1 0>,
<DCC_READ 0xb2c1218 1 0>,
<DCC_READ 0xb2c122c 1 0>,
<DCC_READ 0xb2c1240 1 0>,
<DCC_READ 0xb2c1254 1 0>,
<DCC_READ 0xb2c1208 1 0>,
<DCC_READ 0xb2c121c 1 0>,
<DCC_READ 0xb2c1230 1 0>,
<DCC_READ 0xb2c1244 1 0>,
<DCC_READ 0xb2c1258 1 0>,
<DCC_READ 0xb2c4510 2 0>,
<DCC_READ 0xb2c0010 2 0>,
<DCC_READ 0xb2c0900 2 0>,
<DCC_READ 0x04082028 1 0>,
<DCC_READ 0x18a00c 1 0>,
<DCC_READ 0x04080044 1 0>,
<DCC_READ 0x04080304 1 0>,
<DCC_READ 0x41a802c 1 0>,
<DCC_READ 0x4200010 3 0>,
<DCC_READ 0x4200030 1 0>,
<DCC_READ 0x4200038 1 0>,
<DCC_READ 0x4200040 1 0>,
<DCC_READ 0x4200048 1 0>,
<DCC_READ 0x42000d0 1 0>,
<DCC_READ 0x4200210 1 0>,
<DCC_READ 0x4200230 1 0>,
<DCC_READ 0x4200250 1 0>,
<DCC_READ 0x4200270 1 0>,
<DCC_READ 0x4200290 1 0>,
<DCC_READ 0x42002b0 1 0>,
<DCC_READ 0x4200208 1 0>,
<DCC_READ 0x4200228 1 0>,
<DCC_READ 0x4200248 1 0>,
<DCC_READ 0x4200268 1 0>,
<DCC_READ 0x4200288 1 0>,
<DCC_READ 0x42002a8 1 0>,
<DCC_READ 0x420020c 1 0>,
<DCC_READ 0x420022c 1 0>,
<DCC_READ 0x420024c 1 0>,
<DCC_READ 0x420026c 1 0>,
<DCC_READ 0x420028c 1 0>,
<DCC_READ 0x42002ac 1 0>,
<DCC_READ 0x4200400 3 0>,
<DCC_READ 0x4200d04 1 0>,
<DCC_READ 0x4130010 3 0>,
<DCC_READ 0x4130210 1 0>,
<DCC_READ 0x4130230 1 0>,
<DCC_READ 0x4130250 1 0>,
<DCC_READ 0x4130270 1 0>,
<DCC_READ 0x4130290 1 0>,
<DCC_READ 0x41302b0 1 0>,
<DCC_READ 0x4130208 1 0>,
<DCC_READ 0x4130228 1 0>,
<DCC_READ 0x4130248 1 0>,
<DCC_READ 0x4130268 1 0>,
<DCC_READ 0x4130288 1 0>,
<DCC_READ 0x41302a8 1 0>,
<DCC_READ 0x413020c 1 0>,
<DCC_READ 0x413022c 1 0>,
<DCC_READ 0x413024c 1 0>,
<DCC_READ 0x413026c 1 0>,
<DCC_READ 0x413028c 1 0>,
<DCC_READ 0x41302ac 1 0>,
<DCC_READ 0x4130400 3 0>,
<DCC_READ 0xb254520 1 0>,
<DCC_READ 0xb251020 2 0>,
<DCC_READ 0xb251030 1 0>,
<DCC_READ 0xb251200 1 0>,
<DCC_READ 0xb251214 1 0>,
<DCC_READ 0xb251228 1 0>,
<DCC_READ 0xb25123c 1 0>,
<DCC_READ 0xb251250 1 0>,
<DCC_READ 0xb251204 1 0>,
<DCC_READ 0xb251218 1 0>,
<DCC_READ 0xb25122c 1 0>,
<DCC_READ 0xb251240 1 0>,
<DCC_READ 0xb251254 1 0>,
<DCC_READ 0xb251208 1 0>,
<DCC_READ 0xb25121c 1 0>,
<DCC_READ 0xb251230 1 0>,
<DCC_READ 0xb251244 1 0>,
<DCC_READ 0xb251258 1 0>,
<DCC_READ 0xb254510 2 0>,
<DCC_READ 0xb250010 2 0>,
<DCC_READ 0xb250900 2 0>,
<DCC_READ 0x03002028 1 0>,
<DCC_READ 0x03500010 3 0>,
<DCC_READ 0x03500030 1 0>,
<DCC_READ 0x03500038 1 0>,
<DCC_READ 0x03500040 1 0>,
<DCC_READ 0x03500048 1 0>,
<DCC_READ 0x035000d0 1 0>,
<DCC_READ 0x03500210 1 0>,
<DCC_READ 0x03500230 1 0>,
<DCC_READ 0x03500250 1 0>,
<DCC_READ 0x03500270 1 0>,
<DCC_READ 0x03500290 1 0>,
<DCC_READ 0x035002b0 1 0>,
<DCC_READ 0x03500208 1 0>,
<DCC_READ 0x03500228 1 0>,
<DCC_READ 0x03500248 1 0>,
<DCC_READ 0x03500268 1 0>,
<DCC_READ 0x03500288 1 0>,
<DCC_READ 0x035002a8 1 0>,
<DCC_READ 0x0350020c 1 0>,
<DCC_READ 0x0350022c 1 0>,
<DCC_READ 0x0350024c 1 0>,
<DCC_READ 0x0350026c 1 0>,
<DCC_READ 0x0350028c 1 0>,
<DCC_READ 0x035002ac 1 0>,
<DCC_READ 0x03500400 3 0>,
<DCC_READ 0x03500d04 1 0>,
<DCC_READ 0x030b0010 3 0>,
<DCC_READ 0x030b0210 1 0>,
<DCC_READ 0x030b0230 1 0>,
<DCC_READ 0x030b0250 1 0>,
<DCC_READ 0x030b0270 1 0>,
<DCC_READ 0x030b0290 1 0>,
<DCC_READ 0x030b02b0 1 0>,
<DCC_READ 0x030b0208 1 0>,
<DCC_READ 0x030b0228 1 0>,
<DCC_READ 0x030b0248 1 0>,
<DCC_READ 0x030b0268 1 0>,
<DCC_READ 0x030b0288 1 0>,
<DCC_READ 0x030b02a8 1 0>,
<DCC_READ 0x030b020c 1 0>,
<DCC_READ 0x030b022c 1 0>,
<DCC_READ 0x030b024c 1 0>,
<DCC_READ 0x030b026c 1 0>,
<DCC_READ 0x030b028c 1 0>,
<DCC_READ 0x030b02ac 1 0>,
<DCC_READ 0x030b0400 3 0>,
<DCC_READ 0xb2b4520 1 0>,
<DCC_READ 0xb2b1020 2 0>,
<DCC_READ 0xb2b1030 1 0>,
<DCC_READ 0xb2b1200 1 0>,
<DCC_READ 0xb2b1214 1 0>,
<DCC_READ 0xb2b1228 1 0>,
<DCC_READ 0xb2b123c 1 0>,
<DCC_READ 0xb2b1250 1 0>,
<DCC_READ 0xb2b1204 1 0>,
<DCC_READ 0xb2b1218 1 0>,
<DCC_READ 0xb2b122c 1 0>,
<DCC_READ 0xb2b1240 1 0>,
<DCC_READ 0xb2b1254 1 0>,
<DCC_READ 0xb2b1208 1 0>,
<DCC_READ 0xb2b121c 1 0>,
<DCC_READ 0xb2b1230 1 0>,
<DCC_READ 0xb2b1244 1 0>,
<DCC_READ 0xb2b1258 1 0>,
<DCC_READ 0xb2b4510 2 0>,
<DCC_READ 0xb2b0010 1 0>,
<DCC_READ 0xb2b0900 1 0>,
<DCC_READ 0xa302028 1 0>,
<DCC_READ 0xa0a4010 3 0>,
<DCC_READ 0xa0a4030 1 0>,
<DCC_READ 0xa0a4038 1 0>,
<DCC_READ 0xa0a4040 2 0>,
<DCC_READ 0xa0a40d0 1 0>,
<DCC_READ 0xa0a4210 1 0>,
<DCC_READ 0xa0a4230 1 0>,
<DCC_READ 0xa0a4250 1 0>,
<DCC_READ 0xa0a4270 1 0>,
<DCC_READ 0xa0a4290 1 0>,
<DCC_READ 0xa0a42b0 1 0>,
<DCC_READ 0xa0a4208 1 0>,
<DCC_READ 0xa0a4228 1 0>,
<DCC_READ 0xa0a4248 1 0>,
<DCC_READ 0xa0a4268 1 0>,
<DCC_READ 0xa0a4288 1 0>,
<DCC_READ 0xa0a42a8 1 0>,
<DCC_READ 0xa0a420c 1 0>,
<DCC_READ 0xa0a422c 1 0>,
<DCC_READ 0xa0a424c 1 0>,
<DCC_READ 0xa0a426c 1 0>,
<DCC_READ 0xa0a428c 1 0>,
<DCC_READ 0xa0a42ac 1 0>,
<DCC_READ 0xa0a4400 2 0>,
<DCC_READ 0xa0a4d04 1 0>,
<DCC_READ 0xa3b0010 3 0>,
<DCC_READ 0xa3b0210 1 0>,
<DCC_READ 0xa3b0230 1 0>,
<DCC_READ 0xa3b0250 1 0>,
<DCC_READ 0xa3b0270 1 0>,
<DCC_READ 0xa3b0290 1 0>,
<DCC_READ 0xa3b02b0 1 0>,
<DCC_READ 0xa3b0208 1 0>,
<DCC_READ 0xa3b0228 1 0>,
<DCC_READ 0xa3b0248 1 0>,
<DCC_READ 0xa3b0268 1 0>,
<DCC_READ 0xa3b0288 1 0>,
<DCC_READ 0xa3b02a8 1 0>,
<DCC_READ 0xa3b020c 1 0>,
<DCC_READ 0xa3b022c 1 0>,
<DCC_READ 0xa3b024c 1 0>,
<DCC_READ 0xa3b026c 1 0>,
<DCC_READ 0xa3b028c 1 0>,
<DCC_READ 0xa3b02ac 1 0>,
<DCC_READ 0xa3b0400 3 0>,
<DCC_READ 0x3500d00 3 0>,
<DCC_READ 0x3500d10 4 0>,
<DCC_READ 0x3500fb0 4 0>,
<DCC_READ 0x3501250 4 0>,
<DCC_READ 0x35014f0 4 0>,
<DCC_READ 0x3501790 4 0>,
<DCC_READ 0x3501a30 4 0>,
<DCC_READ 0x3503d44 4 0>,
<DCC_READ 0x35000d0 3 0>,
<DCC_READ 0x3500100 1 0>,
<DCC_READ 0x3500d3c 1 0>,
<DCC_READ 0xa0a40d0 3 0>,
<DCC_READ 0xa0a4100 1 0>,
<DCC_READ 0xa0a4d3c 1 0>,
<DCC_READ 0xa0a7d44 4 0>,
<DCC_READ 0xa0a4d00 3 0>,
<DCC_READ 0x8a02028 1 0>,
<DCC_READ 0x8b00000 1 0>,
<DCC_READ 0x8b00004 1 0>,
<DCC_READ 0x8b00010 1 0>,
<DCC_READ 0x8b00014 1 0>,
<DCC_READ 0x8b00018 1 0>,
<DCC_READ 0x8b0001c 1 0>,
<DCC_READ 0x8b00020 1 0>,
<DCC_READ 0x8b00024 1 0>,
<DCC_READ 0x8b00028 1 0>,
<DCC_READ 0x8b0002c 1 0>,
<DCC_READ 0x8b00030 1 0>,
<DCC_READ 0x8b00034 1 0>,
<DCC_READ 0x8b00038 1 0>,
<DCC_READ 0x8b0003c 1 0>,
<DCC_READ 0x8b00040 1 0>,
<DCC_READ 0x8b00044 1 0>,
<DCC_READ 0x8b00048 1 0>,
<DCC_READ 0x8b000d0 1 0>,
<DCC_READ 0x8b000d8 1 0>,
<DCC_READ 0x8b00100 1 0>,
<DCC_READ 0x8b00104 1 0>,
<DCC_READ 0x8b00108 1 0>,
<DCC_READ 0x8b00200 1 0>,
<DCC_READ 0x8b00204 1 0>,
<DCC_READ 0x8b00224 1 0>,
<DCC_READ 0x8b00244 1 0>,
<DCC_READ 0x8b00264 1 0>,
<DCC_READ 0x8b00284 1 0>,
<DCC_READ 0x8b002a4 1 0>,
<DCC_READ 0x8b00208 1 0>,
<DCC_READ 0x8b00228 1 0>,
<DCC_READ 0x8b00248 1 0>,
<DCC_READ 0x8b00268 1 0>,
<DCC_READ 0x8b00288 1 0>,
<DCC_READ 0x8b002a8 1 0>,
<DCC_READ 0x8b0020c 1 0>,
<DCC_READ 0x8b0022c 1 0>,
<DCC_READ 0x8b0024c 1 0>,
<DCC_READ 0x8b0026c 1 0>,
<DCC_READ 0x8b0028c 1 0>,
<DCC_READ 0x8b002ac 1 0>,
<DCC_READ 0x8b00210 1 0>,
<DCC_READ 0x8b00230 1 0>,
<DCC_READ 0x8b00250 1 0>,
<DCC_READ 0x8b00270 1 0>,
<DCC_READ 0x8b00290 1 0>,
<DCC_READ 0x8b002b0 1 0>,
<DCC_READ 0x8b00400 1 0>,
<DCC_READ 0x8b00404 1 0>,
<DCC_READ 0x8b00408 1 0>,
<DCC_READ 0x8b00460 1 0>,
<DCC_READ 0x8b00464 1 0>,
<DCC_READ 0x8b004a0 1 0>,
<DCC_READ 0x8b004a4 1 0>,
<DCC_READ 0x8b004a8 1 0>,
<DCC_READ 0x8b004ac 1 0>,
<DCC_READ 0x8b004b0 1 0>,
<DCC_READ 0x8b004b4 1 0>,
<DCC_READ 0x8b004b8 1 0>,
<DCC_READ 0x8ab0000 1 0>,
<DCC_READ 0x8ab0004 1 0>,
<DCC_READ 0x8ab0010 1 0>,
<DCC_READ 0x8ab0014 1 0>,
<DCC_READ 0x8ab0018 1 0>,
<DCC_READ 0x8ab00d0 1 0>,
<DCC_READ 0x8ab00d8 1 0>,
<DCC_READ 0x8ab0100 1 0>,
<DCC_READ 0x8ab0104 1 0>,
<DCC_READ 0x8ab0108 1 0>,
<DCC_READ 0x8ab0200 1 0>,
<DCC_READ 0x8ab0204 1 0>,
<DCC_READ 0x8ab0224 1 0>,
<DCC_READ 0x8ab0244 1 0>,
<DCC_READ 0x8ab0264 1 0>,
<DCC_READ 0x8ab0284 1 0>,
<DCC_READ 0x8ab02a4 1 0>,
<DCC_READ 0x8ab0208 1 0>,
<DCC_READ 0x8ab0228 1 0>,
<DCC_READ 0x8ab0248 1 0>,
<DCC_READ 0x8ab0268 1 0>,
<DCC_READ 0x8ab0288 1 0>,
<DCC_READ 0x8ab02a8 1 0>,
<DCC_READ 0x8ab020c 1 0>,
<DCC_READ 0x8ab022c 1 0>,
<DCC_READ 0x8ab024c 1 0>,
<DCC_READ 0x8ab026c 1 0>,
<DCC_READ 0x8ab028c 1 0>,
<DCC_READ 0x8ab02ac 1 0>,
<DCC_READ 0x8ab0210 1 0>,
<DCC_READ 0x8ab0230 1 0>,
<DCC_READ 0x8ab0250 1 0>,
<DCC_READ 0x8ab0270 1 0>,
<DCC_READ 0x8ab0290 1 0>,
<DCC_READ 0x8ab02b0 1 0>,
<DCC_READ 0x8ab0400 1 0>,
<DCC_READ 0x8ab0404 1 0>,
<DCC_READ 0x8ab0408 1 0>,
<DCC_READ 0x8ab0460 1 0>,
<DCC_READ 0x8ab0464 1 0>,
<DCC_READ 0x8ab04a0 1 0>,
<DCC_READ 0x8ab04a4 1 0>,
<DCC_READ 0x8ab04a8 1 0>,
<DCC_READ 0x8ab04ac 1 0>,
<DCC_READ 0x8ab04b0 1 0>,
<DCC_READ 0x8ab04b4 1 0>,
<DCC_READ 0x8ab04b8 1 0>,
<DCC_READ 0xaa10504 1 0>,
<DCC_READ 0xaa10508 1 0>,
<DCC_READ 0xaa10510 1 0>,
<DCC_READ 0xaa10520 1 0>,
<DCC_READ 0xaa10524 1 0>,
<DCC_READ 0xaa10528 1 0>,
<DCC_READ 0xaa1052c 1 0>,
<DCC_READ 0xaa10530 1 0>,
<DCC_READ 0xaa10534 1 0>,
<DCC_READ 0xaa10538 1 0>,
<DCC_READ 0xaa1053c 1 0>,
<DCC_READ 0xaa10300 1 0>,
<DCC_READ 0xaa10010 1 0>,
<DCC_READ 0xaa10020 1 0>;
};
};
qcom,msm-imem@146aa000 {
compatible = "qcom,msm-imem";
reg = <0x146aa000 0x1000>;
ranges = <0x0 0x146aa000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 0xc8>;
};
pil@6dc {
compatible = "qcom,msm-imem-pil-disable-timeout";
reg = <0x6dc 0x4>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
jtag_mm0: jtagmm@7040000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7040000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm1: jtagmm@7140000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7140000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm2: jtagmm@7240000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7240000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm3: jtagmm@7340000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7340000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
jtag_mm4: jtagmm@7440000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7440000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU4>;
};
jtag_mm5: jtagmm@7540000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7540000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU5>;
};
jtag_mm6: jtagmm@7640000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7640000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU6>;
};
jtag_mm7: jtagmm@7740000 {
compatible = "qcom,jtagv8-mm";
reg = <0x7740000 0x1000>;
reg-names = "etm-base";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,coresight-jtagmm-cpu = <&CPU7>;
};
eud: qcom,msm-eud@88e0000 {
compatible = "qcom,msm-eud";
interrupt-names = "eud_irq";
interrupt-parent = <&pdc>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x088e0000 0x2000>,
<0x088e2000 0x1000>;
reg-names = "eud_base", "eud_mode_mgr2";
qcom,secure-eud-en;
status = "ok"
};
qcom,memshare {
compatible = "qcom,memshare";
qcom,client_1 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x0>;
qcom,client-id = <0>;
qcom,allocate-boot-time;
label = "modem";
};
qcom,client_2 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x0>;
qcom,client-id = <2>;
label = "modem";
};
qcom,client_3 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x500000>;
memory-region = <&memshare_mem>;
qcom,client-id = <1>;
qcom,allocate-on-request;
label = "modem";
};
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <76800000>;
clock-output-names = "xo_board";
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
pcie_0_pipe_clk: pcie-0-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
};
pcie_1_pipe_clk: pcie-1-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_1_pipe_clk";
#clock-cells = <0>;
};
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <0>;
};
};
aopcc: qcom,aopcc {
compatible = "qcom,aop-qmp-clk";
mboxes = <&qmp_aop 0>;
mbox-names = "qdss_clk";
#clock-cells = <1>;
qcom,clk-stop-bimc-log;
};
gcc: clock-controller@100000 {
compatible = "qcom,yupik-gcc", "syscon";
reg = <0x100000 0x1f0000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo",
"sleep_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
protected-clocks = <GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, <GCC_DDRSS_PCIE_SF_CLK>,
<GCC_PCIE0_PHY_RCHNG_CLK>, <GCC_PCIE1_PHY_RCHNG_CLK>,
<GCC_PCIE_0_AUX_CLK>, <GCC_PCIE_0_AUX_CLK_SRC>,
<GCC_PCIE_0_CFG_AHB_CLK>, <GCC_PCIE_0_MSTR_AXI_CLK>,
<GCC_PCIE_0_PHY_RCHNG_CLK_SRC>, <GCC_PCIE_0_PIPE_CLK>,
<GCC_PCIE_0_PIPE_CLK_SRC>, <GCC_PCIE_0_SLV_AXI_CLK>,
<GCC_PCIE_0_SLV_Q2A_AXI_CLK>, <GCC_PCIE_1_AUX_CLK>,
<GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>,
<GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>,
<GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>,
<GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<GCC_PCIE_THROTTLE_CORE_CLK>, <GCC_THROTTLE_PCIE_AHB_CLK>,
<GCC_AGGRE_USB3_SEC_AXI_CLK>, <GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<GCC_USB30_SEC_MASTER_CLK>, <GCC_USB30_SEC_MASTER_CLK_SRC>,
<GCC_USB30_SEC_MOCK_UTMI_CLK>, <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>,
<GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>,
<GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>,
<GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>,
<GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>,
<GCC_AGGRE_NOC_PCIE_TBU_CLK>, <GCC_PCIE_CLKREF_EN>;
#clock-cells = <1>;
#reset-cells = <1>;
};
camcc: clock-controller@ad00000 {
compatible = "qcom,yupik-camcc", "syscon";
reg = <0xad00000 0x10000>;
reg-names = "cc_base";
vdd_mx-supply = <&VDD_MX_LEVEL>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "cfg_ahb";
#clock-cells = <1>;
#reset-cells = <1>;
};
dispcc: clock-controller@af00000 {
compatible = "qcom,yupik-dispcc", "syscon";
reg = <0xaf00000 0x20000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&gcc GCC_DISP_AHB_CLK>;
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk","cfg_ahb";
#clock-cells = <1>;
#reset-cells = <1>;
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,yupik-gpucc", "syscon";
reg = <0x3d90000 0x9000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src", "cfg_ahb";
#clock-cells = <1>;
#reset-cells = <1>;
};
videocc: clock-controller@aaf0000 {
compatible = "qcom,yupik-videocc", "syscon";
reg = <0xaaf0000 0x10000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>, <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "cfg_ahb";
#clock-cells = <1>;
#reset-cells = <1>;
};
apsscc: syscon@182a0000 {
compatible = "syscon";
reg = <0x182a0000 0x1c>;
};
mccc: syscon@90ba000 {
compatible = "syscon";
reg = <0x90ba000 0x54>;
};
debugcc: debug-clock-controller@0 {
compatible = "qcom,yupik-debugcc";
qcom,gcc = <&gcc>;
qcom,camcc = <&camcc>;
qcom,dispcc = <&dispcc>;
qcom,gpucc = <&gpucc>;
qcom,videocc = <&videocc>;
qcom,apsscc = <&apsscc>;
qcom,mccc = <&mccc>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo_clk_src";
#clock-cells = <1>;
};
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw-epss";
reg = <0x18591000 0x1000>, <0x18592000 0x1000>,
<0x18593000 0x1000>;
reg-names = "freq-domain0", "freq-domain1",
"freq-domain2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
qcom,lut-row-size = <4>;
qcom,skip-enable-check;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int";
qcom,sdpm-cx-mx-1 = <0x00636f08 0x4>;
qcom,sdpm-cx-mx-2 = <0x00636f0c 0x4>;
#freq-domain-cells = <2>;
};
qcom,cpufreq-hw-debug@18591000 {
compatible = "qcom,cpufreq-hw-epss-debug";
reg = <0x18591000 0x800>;
reg-names = "domain-top";
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>,
<&cpufreq_hw 2>;
};
qcom,venus@aab0000 {
compatible = "qcom,pil-tz-generic";
reg = <0xaab0000 0x2000>;
vdd-supply = <&video_cc_mvsc_gdsc>;
qcom,proxy-reg-names = "vdd";
qcom,complete-ramdump;
clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
<&videocc VIDEO_CC_VENUS_AHB_CLK>;
clock-names = "core", "ahb";
qcom,proxy-clock-names = "core", "ahb";
qcom,core-freq = <200000000>;
qcom,ahb-freq = <200000000>;
qcom,pas-id = <9>;
interconnect-names = "pil-venus";
interconnects = <&mmss_noc MASTER_VIDEO_P0
&mc_virt SLAVE_EBI1>;
qcom,proxy-timeout-ms = <100>;
qcom,firmware-name = "venus";
memory-region = <&pil_video_mem>;
};
qcom_hwkm: hwkm@10c0000 {
compatible = "qcom,hwkm";
reg = <0x10c0000 0x9000>, <0x1d90000 0x9000>;
reg-names = "km_master", "ice_slave";
qcom,enable-hwkm-clk;
clock-names = "km_clk_src";
clocks = <&rpmhcc RPMH_HWKM_CLK>;
qcom,op-freq-hz = <75000000>;
};
ufsphy_mem: ufsphy_mem@1d87000 {
reg = <0x1d87000 0xe00>;
reg-names = "phy_mem";
#phy-cells = <0>;
lanes-per-direction = <2>;
clock-names = "ref_clk_src",
"ref_clk",
"ref_aux_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_1_CLKREF_EN>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
resets = <&ufshc_mem 0>;
status = "disabled";
};
icnss2: qcom,wcn6750 {
compatible = "qcom,wcn6750";
reg = <0x17a10040 0x0>,
<0xb0000000 0x10000>,
<0xb2e5510 0x5c0>;
reg-names = "msi_addr", "smmu_iova_ipa", "tcs_cmd";
iommus = <&apps_smmu 0x1c00 0x1>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
qcom,iommu-dma = "fastmap";
qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
qcom,iommu-geometry = <0xa0000000 0x10010000>;
qcom,wlan-msa-fixed-region = <&wlan_fw_mem>;
qcom,cmd_db_name = "smpb7";
cnss-daemon-support;
dma-coherent;
qcom,fw-prefix;
vdd-cx-mx-supply = <&S7B>;
qcom,vdd-cx-mx-config = <824000 1120000 0 0 1>;
vdd-1.8-xo-supply = <&S1B>;
qcom,vdd-1.8-xo-config = <1872000 2040000 0 0 0>;
vdd-1.3-rfa-supply = <&S8B>;
qcom,vdd-1.3-rfa-config = <1256000 1500000 0 0 0>;
qcom,smem-states = <&smp2p_wlan_1_out 0>;
qcom,smem-state-names = "wlan-smp2p-out";
icnss_cdev_apss: qcom,icnss_cdev1 {
#cooling-cells = <2>;
};
icnss_cdev_wpss: qcom,icnss_cdev2 {
#cooling-cells = <2>;
};
qcom,smp2p_map_wlan_1_in {
interrupts-extended = <&smp2p_wlan_1_in 0 0>,
<&smp2p_wlan_1_in 1 0>;
interrupt-names = "qcom,smp2p-force-fatal-error",
"qcom,smp2p-early-crash-ind";
};
};
bluetooth: bt_wcn6750 {
compatible = "qcom,wcn6750-bt";
pinctrl-names = "default";
pinctrl-0 = <&bt_en_sleep>;
qcom,bt-reset-gpio = <&tlmm 85 0>; /* BT_EN */
qcom,bt-sw-ctrl-gpio = <&tlmm 86 0>; /* SW_CTRL */
qcom,wl-reset-gpio = <&tlmm 84 0>; /* WL_EN */
qcom,bt-vdd-io-supply = <&L19B>; /* IO */
qcom,bt-vdd-aon-supply = <&S7B>;
qcom,bt-vdd-dig-supply = <&S7B>;
qcom,bt-vdd-rfacmn-supply = <&S7B>;
qcom,bt-vdd-rfa-0p8-supply = <&S7B>;
qcom,bt-vdd-rfa1-supply = <&S1B>; /*RFA 1p7*/
qcom,bt-vdd-rfa2-supply = <&S8B>; /*RFA 1p2*/
qcom,bt-vdd-ipa-2p2-supply = <&S1C>; /*IPA 2p2*/
qcom,bt-vdd-asd-supply = <&L11C>;
/* max voltage are set to regulator max voltage supported */
qcom,bt-vdd-io-config = <1800000 2000000 0 1>;
qcom,bt-vdd-aon-config = <824000 1120000 0 1>;
qcom,bt-vdd-dig-config = <824000 1120000 0 1>;
qcom,bt-vdd-rfacmn-config = <824000 1120000 0 1>;
qcom,bt-vdd-rfa-0p8-config = <824000 1120000 0 1>;
qcom,bt-vdd-rfa1-config = <1872000 2040000 0 1>;
qcom,bt-vdd-rfa2-config = <1256000 1500000 0 1>;
qcom,bt-vdd-ipa-2p2-config = <2200000 2210000 0 1>;
qcom,bt-vdd-asd-config = <2800000 3544000 0 1>;
};
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>,
<0x1d88000 0x8000>,
<0x1d90000 0x9000>;
reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
#reset-cells = <1>;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_UFS_MEM_CFG>;
interconnect-names = "ufs-ddr", "cpu-ufs";
qcom,ufs-bus-bw,name = "ufshc_mem";
qcom,ufs-bus-bw,num-cases = <26>;
qcom,ufs-bus-bw,num-paths = <2>;
qcom,ufs-bus-bw,vectors-KBps =
/*
* During HS G3 UFS runs at nominal voltage corner, vote
* higher bandwidth to push other buses in the data path
* to run at nominal to achieve max throughput.
* 4GBps pushes BIMC to run at nominal.
* 200MBps pushes CNOC to run at nominal.
* Vote for half of this bandwidth for HS G3 1-lane.
* For max bandwidth, vote high enough to push the buses
* to run in turbo voltage corner.
*/
<0 0>, <0 0>, /* No vote */
<922 0>, <1000 0>, /* PWM G1 */
<1844 0>, <1000 0>, /* PWM G2 */
<3688 0>, <1000 0>, /* PWM G3 */
<7376 0>, <1000 0>, /* PWM G4 */
<1844 0>, <1000 0>, /* PWM G1 L2 */
<3688 0>, <1000 0>, /* PWM G2 L2 */
<7376 0>, <1000 0>, /* PWM G3 L2 */
<14752 0>, <1000 0>, /* PWM G4 L2 */
<127796 0>, <1000 0>, /* HS G1 RA */
<255591 0>, <1000 0>, /* HS G2 RA */
<2097152 0>, <102400 0>, /* HS G3 RA */
<4194304 0>, <204800 0>, /* HS G4 RA */
<255591 0>, <1000 0>, /* HS G1 RA L2 */
<511181 0>, <1000 0>, /* HS G2 RA L2 */
<4194304 0>, <204800 0>, /* HS G3 RA L2 */
<8388608 0>, <409600 0>, /* HS G4 RA L2 */
<149422 0>, <1000 0>, /* HS G1 RB */
<298189 0>, <1000 0>, /* HS G2 RB */
<2097152 0>, <102400 0>, /* HS G3 RB */
<4194304 0>, <204800 0>, /* HS G4 RB */
<298189 0>, <1000 0>, /* HS G1 RB L2 */
<596378 0>, <1000 0>, /* HS G2 RB L2 */
/* As UFS working in HS G3 RB L2 mode, aggregated
* bandwidth (AB) should take care of providing
* optimum throughput requested. However, as tested,
* in order to scale up CNOC clock, instantaneous
* bindwidth (IB) needs to be given a proper value too.
*/
<4194304 0>, <204800 409600>, /* HS G3 RB L2 */
<8388608 0>, <409600 409600>, /* HS G4 RB L2 */
<7643136 0>, <307200 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
"MAX";
reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
iommus = <&apps_smmu 0x80 0x0>;
qcom,iommu-dma = "fastmap";
dma-coherent;
rpm-level = <3>;
/*
* UFS2.2 is drawing 40mA current during APPS PC.
* Issue is seen only if PX10 is turned off and Vccq2 is ON.
* Since Vccq2 is always-on supply we can't turn it off,
* so don't turn off PX10, by updating spm_lvl to 3.
* In sleep state (spm-lvl=3) its drawing only .5mA.
*/
spm-level = <3>;
status = "disabled";
qos0 {
mask = <0xf0>;
vote = <65>;
};
qos1 {
mask = <0x0f>;
vote = <59>;
};
};
cpu_pmu: cpu-pmu {
compatible = "arm,armv8-pmuv3";
qcom,irq-is-percpu;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
qcom,chd {
compatible = "qcom,core-hang-detect";
label = "core";
qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058
0x18040058 0x18050058 0x18060058 0x18070058>;
qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060
0x18040060 0x18050060 0x18060060 0x18070060>;
};
dload_mode {
compatible = "qcom,dload-mode";
};
kryo-erp {
compatible = "arm,arm64-kryo-cpu-erp";
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;
};
qcom,mpm2-sleep-counter@c221000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0xc221000 0x1000>;
clock-frequency = <32768>;
};
cache-controller@9200000 {
compatible = "qcom,yupik-llcc","qcom,llcc-v2";
reg = <0x9200000 0xd0000>, <0x9600000 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
cap-based-alloc-and-pwr-collapse;
clocks = <&aopcc QDSS_CLK>;
clock-names = "qdss_clk";
};
clk_virt: interconnect {
compatible = "qcom,yupik-clk_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
cnoc2: interconnect@1500000 {
reg = <0x1500000 0x1000>;
compatible = "qcom,yupik-cnoc2";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
cnoc3: interconnect@1502000 {
reg = <0x1502000 0x1000>;
compatible = "qcom,yupik-cnoc3";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@1580000 {
reg = <0x1580000 0x4>;
compatible = "qcom,yupik-mc_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp";
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
};
system_noc: interconnect@1680000 {
reg = <0x1680000 0x15480>;
compatible = "qcom,yupik-system_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,yupik-aggre1_noc";
reg = <0x016e0000 0x1c080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
};
aggre2_noc: interconnect@1700000 {
reg = <0x1700000 0x2b080>;
compatible = "qcom,yupik-aggre2_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&rpmhcc RPMH_IPA_CLK>;
};
mmss_noc: interconnect@1740000 {
reg = <0x1740000 0x1e080>;
compatible = "qcom,yupik-mmss_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp";
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
};
lpass_ag_noc: interconnect@3c40000 {
reg = <0x03c40000 0xf080>;
compatible = "qcom,yupik-lpass_ag_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
dc_noc: interconnect@90e0000 {
reg = <0x90e0000 0x5080>;
compatible = "qcom,yupik-dc_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect@9100000 {
reg = <0x9100000 0xe2200>;
compatible = "qcom,yupik-gem_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos", "disp";
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
};
nsp_noc: interconnect@a0c0000 {
reg = <0x0a0c0000 0x10000>;
compatible = "qcom,yupik-nsp_noc";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
epss_l3_cpu: l3_cpu@18590000 {
reg = <0x18590000 0x4000>;
compatible = "qcom,lahaina-epss-l3-cpu";
#interconnect-cells = <1>;
clock-names = "xo", "alternate";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPLL0>;
};
llcc_pmu: llcc-pmu@9095000 {
compatible = "qcom,llcc-pmu-ver2";
reg = <0x09095000 0x300>;
reg-names = "lagg-base";
};
llcc_bw_opp_table: llcc-bw-opp-table {
compatible = "operating-points-v2";
BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
BW_OPP_ENTRY( 1066, 16); /* 15258 MB/s */
};
ddr_bw_opp_table: ddr-bw-opp-table {
compatible = "operating-points-v2";
BW_OPP_ENTRY_DDR( 200, 4, 0x180); /* 762 MB/s */
BW_OPP_ENTRY_DDR( 451, 4, 0x180); /* 1720 MB/s */
BW_OPP_ENTRY_DDR( 547, 4, 0x180); /* 2086 MB/s */
BW_OPP_ENTRY_DDR( 681, 4, 0x180); /* 2597 MB/s */
BW_OPP_ENTRY_DDR( 768, 4, 0x180); /* 2929 MB/s */
BW_OPP_ENTRY_DDR( 1017, 4, 0x80); /* 3879 MB/s */
BW_OPP_ENTRY_DDR( 1353, 4, 0x80); /* 5161 MB/s */
BW_OPP_ENTRY_DDR( 1555, 4, 0x180); /* 5931 MB/s */
BW_OPP_ENTRY_DDR( 1708, 4, 0x180); /* 6515 MB/s */
BW_OPP_ENTRY_DDR( 2092, 4, 0x180); /* 7980 MB/s */
BW_OPP_ENTRY_DDR( 2133, 4, 0x80); /* 8136 MB/s */
BW_OPP_ENTRY_DDR( 2736, 4, 0x100); /* 10437 MB/s */
BW_OPP_ENTRY_DDR( 3196, 4, 0x100); /* 12191 MB/s */
};
qoslat_opp_table: qoslat-opp-table {
compatible = "operating-points-v2";
opp-1 {
opp-hz = /bits/ 64 < 1 >;
};
opp-2 {
opp-hz = /bits/ 64 < 2 >;
};
};
cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
compatible = "qcom,devfreq-icc";
governor = "bw_hwmon";
interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
compatible = "qcom,bimc-bwmon4";
reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&cpu_cpu_llcc_bw>;
qcom,count-unit = <0x10000>;
};
cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
compatible = "qcom,devfreq-icc-ddr";
governor = "bw_hwmon";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@9091000 {
compatible = "qcom,bimc-bwmon5";
reg = <0x9091000 0x1000>;
reg-names = "base";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&cpu_llcc_ddr_bw>;
qcom,count-unit = <0x10000>;
};
snoop_l3_bw: qcom,snoop-l3-bw {
compatible = "qcom,devfreq-icc-l3bw";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
qcom,bus-width = <32>;
governor = "bw_hwmon";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_SHARED>;
};
snoop_l3_bwmon: qcom,snoop-l3-bwmon@9091000 {
compatible = "qcom,bimc-bwmon4";
reg = <0x90b9100 0x300>, <0x90b9000 0x200>;
reg-names = "base", "global_base";
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
qcom,mport = <0>;
qcom,hw-timer-hz = <19200000>;
qcom,target-dev = <&snoop_l3_bw>;
qcom,count-unit = <0x10000>;
};
cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
compatible = "qcom,devfreq-icc";
governor = "mem_latency";
interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {
compatible = "qcom,devfreq-icc";
governor = "mem_latency";
interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
compatible = "qcom,devfreq-icc-ddr";
governor = "mem_latency";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {
compatible = "qcom,devfreq-icc-ddr";
governor = "mem_latency";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc-ddr";
governor = "compute";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc-ddr";
governor = "compute";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu4_cpu_llcc_latfloor: qcom,cpu4-cpu-llcc-latfloor {
compatible = "qcom,devfreq-icc";
governor = "compute";
interconnects = <&gem_noc MASTER_APPSS_PROC &gem_noc SLAVE_LLCC>;
qcom,active-only;
operating-points-v2 = <&llcc_bw_opp_table>;
};
cpu7_cpu_ddr_latfloor: qcom,cpu7-cpu-ddr-latfloor {
compatible = "qcom,devfreq-icc-ddr";
governor = "compute";
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
qcom,active-only;
operating-points-v2 = <&ddr_bw_opp_table>;
};
cpu7_cpu_l3_latfloor: qcom,cpu7-cpu-l3-latfloor {
compatible = "qcom,devfreq-icc-l3";
reg = <0x18590100 0xa0>;
reg-names = "ftbl-base";
governor = "compute";
interconnects =
<&epss_l3_cpu MASTER_EPSS_L3_APPS
&epss_l3_cpu SLAVE_EPSS_L3_SHARED>;
};
cpu4_cpu_ddr_qoslat: qcom,cpu4-cpu-ddr-qoslat {
compatible = "qcom,devfreq-qoslat";
governor = "mem_latency";
operating-points-v2 = <&qoslat_opp_table>;
mboxes = <&qmp_aop 0>;
};
cpu7_cpu_ddr_qoslatfloor: qcom,cpu7-cpu-ddr-qoslatfloor {
compatible = "qcom,devfreq-qoslat";
governor = "mem_latency";
operating-points-v2 = <&qoslat_opp_table>;
mboxes = <&qmp_aop 0>;
};
cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
compatible = "qcom,arm-memlat-cpugrp";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7>;
cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,target-dev = <&cpu0_cpu_llcc_lat>;
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,cachemiss-ev = <0x2A>;
qcom,core-dev-table =
< 1152000 MHZ_TO_MBPS( 300, 16) >,
< 1516800 MHZ_TO_MBPS( 466, 16) >,
< 1804800 MHZ_TO_MBPS( 600, 16) >;
};
cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,target-dev = <&cpu0_llcc_ddr_lat>;
qcom,cachemiss-ev = <0x1000>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 940800 MHZ_TO_MBPS( 451, 4) >,
< 1152000 MHZ_TO_MBPS( 547, 4) >,
< 1516800 MHZ_TO_MBPS( 768, 4) >,
< 1804800 MHZ_TO_MBPS( 1017, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 940800 MHZ_TO_MBPS( 451, 4) >,
< 1152000 MHZ_TO_MBPS( 547, 4) >,
< 1516800 MHZ_TO_MBPS( 768, 4) >,
< 1804800 MHZ_TO_MBPS( 1555, 4) >;
};
};
cpu0_computemon: qcom,cpu0-computemon {
compatible = "qcom,arm-compute-mon";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
qcom,core-dev-table =
< 1152000 MHZ_TO_MBPS( 451, 4) >,
< 1516800 MHZ_TO_MBPS( 547, 4) >,
< 1804800 MHZ_TO_MBPS( 768, 4) >;
};
cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,target-dev = <&cpu4_cpu_llcc_lat>;
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cachemiss-ev = <0x2A>;
qcom,core-dev-table =
< 691200 MHZ_TO_MBPS( 300, 16) >,
< 940800 MHZ_TO_MBPS( 466, 16) >,
< 1228800 MHZ_TO_MBPS( 600, 16) >,
< 1651200 MHZ_TO_MBPS( 806, 16) >,
< 2400000 MHZ_TO_MBPS( 933, 16) >,
< 2707200 MHZ_TO_MBPS( 1066, 16) >;
};
cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&cpu4_llcc_ddr_lat>;
qcom,cachemiss-ev = <0x1000>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 691200 MHZ_TO_MBPS( 451, 4) >,
< 940800 MHZ_TO_MBPS( 547, 4) >,
< 1228800 MHZ_TO_MBPS(1017, 4) >,
< 1651200 MHZ_TO_MBPS(1555, 4) >,
< 2380800 MHZ_TO_MBPS(1708, 4) >,
< 2707200 MHZ_TO_MBPS(2133, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 691200 MHZ_TO_MBPS( 451, 4) >,
< 940800 MHZ_TO_MBPS( 547, 4) >,
< 1228800 MHZ_TO_MBPS( 768, 4) >,
< 1651200 MHZ_TO_MBPS(1555, 4) >,
< 1900800 MHZ_TO_MBPS(1708, 4) >,
< 2380800 MHZ_TO_MBPS(2092, 4) >,
< 2707200 MHZ_TO_MBPS(3196, 4) >;
};
};
cpu4_computemon: qcom,cpu4-computemon {
compatible = "qcom,arm-compute-mon";
qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 691200 MHZ_TO_MBPS( 451, 4) >,
< 1228800 MHZ_TO_MBPS( 547, 4) >,
< 1516800 MHZ_TO_MBPS( 768, 4) >,
< 1651200 MHZ_TO_MBPS(1017, 4) >,
< 1900800 MHZ_TO_MBPS(1555, 4) >,
< 2400000 MHZ_TO_MBPS(1708, 4) >,
< 2707200 MHZ_TO_MBPS(2133, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 691200 MHZ_TO_MBPS( 451, 4) >,
< 1228800 MHZ_TO_MBPS( 547, 4) >,
< 1516800 MHZ_TO_MBPS( 768, 4) >,
< 1651200 MHZ_TO_MBPS(1555, 4) >,
< 1900800 MHZ_TO_MBPS(1708, 4) >,
< 2400000 MHZ_TO_MBPS(2092, 4) >,
< 2707200 MHZ_TO_MBPS(3196, 4) >;
};
};
cpu4_llcc_computemon: qcom,cpu4-llcc-computemon {
compatible = "qcom,arm-compute-mon";
qcom,target-dev = <&cpu4_cpu_llcc_latfloor>;
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,core-dev-table =
< 1900800 MHZ_TO_MBPS( 150, 16) >,
< 2707200 MHZ_TO_MBPS( 600, 16) >;
};
cpu7_computemon: qcom,cpu7-computemon {
compatible = "qcom,arm-compute-mon";
qcom,target-dev = <&cpu7_cpu_ddr_latfloor>;
qcom,cpulist = <&CPU7>;
ddr4-map {
qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
qcom,core-dev-table =
< 2380800 MHZ_TO_MBPS( 451, 4) >,
< 2707200 MHZ_TO_MBPS(2133, 4) >;
};
ddr5-map {
qcom,ddr-type = <DDR_TYPE_LPDDR5>;
qcom,core-dev-table =
< 2380800 MHZ_TO_MBPS( 451, 4) >,
< 2707200 MHZ_TO_MBPS(3196, 4) >;
};
};
cpu7_l3_computemon: qcom,cpu7-l3-computemon {
compatible = "qcom,arm-compute-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu7_cpu_l3_latfloor>;
qcom,core-dev-table =
< 2035200 300000000 >,
< 2707200 1516800000 >;
};
cpu4_qoslatmon: qcom,cpu4-qoslatmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,target-dev = <&cpu4_cpu_ddr_qoslat>;
qcom,cachemiss-ev = <0x1000>;
qcom,core-dev-table =
< 300000 1 >,
< 3000000 2 >;
};
cpu7_qoslatmon: qcom,cpu7-qoslatmon {
compatible = "qcom,arm-memlat-mon";
qcom,cpulist = <&CPU7>;
qcom,target-dev = <&cpu7_cpu_ddr_qoslatfloor>;
qcom,cachemiss-ev = <0x1000>;
qcom,core-dev-table =
< 2035200 1 >,
< 2707200 2 >;
};
};
rimps: qcom,rimps@17C00000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "qcom,rimps";
reg = <0x17C00000 0x10>,
<0x18590000 0x2000>;
#mbox-cells = <1>;
interrupts = <0 62 4>;
};
cpu0_grp: qcom,cpu0_grp {
compatible = "qcom,rimps-memlat-cpugrp";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x185098E0 0x320>;
reg-names = "pmu-base";
cpu0_rimps_l3_latmon: qcom,cpu0-rimps-l3-latmon {
compatible = "qcom,rimps-memlat-mon-l3";
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
qcom,cachemiss-ev = <0x17>;
reg = <0x18590100 0xa0>, <0x18590340 0x4>;
reg-names = "ftbl-base", "perf-base";
qcom,core-dev-table =
< 300000 300000000 >,
< 691200 556800000 >,
< 806400 652800000 >,
< 940800 768000000 >,
< 1152000 844800000 >,
< 1324800 1065600000 >,
< 1516800 1190400000 >,
< 1651200 1305600000 >,
< 1804800 1516800000 >;
};
};
cpu4_grp: qcom,cpu4_grp {
compatible = "qcom,rimps-memlat-cpugrp";
qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x185098E0 0x320>;
reg-names = "pmu-base";
cpu4_rimps_l3_latmon: qcom,cpu4-rimps-l3-latmon {
compatible = "qcom,rimps-memlat-mon-l3";
qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
qcom,cachemiss-ev = <0x17>;
qcom,wb-ev = <0x18>;
qcom,access-ev = <0x2B>;
reg = <0x18590100 0xa0>, <0x18590340 0x4>;
reg-names = "ftbl-base", "perf-base";
qcom,core-dev-table =
< 940800 556800000 >,
< 1228800 768000000 >,
< 1651200 1190400000 >,
< 1900800 1401600000 >,
< 2400000 1516800000 >;
};
};
cpu7_grp: qcom,cpu7_grp {
compatible = "qcom,rimps-memlat-cpugrp";
qcom,cpulist = <&CPU7>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
reg = <0x185098E0 0x320>;
reg-names = "pmu-base";
cpu7_rimps_l3_latmon: qcom,cpu7-rimps-l3-latmon {
compatible = "qcom,rimps-memlat-mon-l3";
qcom,cpulist = <&CPU7>;
qcom,cachemiss-ev = <0x17>;
qcom,wb-ev = <0x18>;
qcom,access-ev = <0x2B>;
reg = <0x18590100 0xa0>, <0x18590340 0x4>;
reg-names = "ftbl-base", "perf-base";
qcom,core-dev-table =
< 1056000 556800000 >,
< 1324800 768000000 >,
< 1766400 1190400000 >,
< 2208000 1401600000 >,
< 2707200 1516800000 >;
};
};
scmi: qcom,scmi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "arm,scmi";
mboxes = <&rimps 0>;
mbox-names = "tx";
shmem = <&cpu_scp_lpri>;
scmi_memlat: protocol@80 {
reg = <0x80>;
#clock-cells = <1>;
};
scmi_perf_lock: protocol@81 {
reg = <0x81>;
#clock-cells = <1>;
};
};
rimps_log: qcom,rimps_log@18509C00 {
compatible = "qcom,rimps-log";
reg = <0x18509C00 0x200>,
<0x18509E00 0x200>;
mboxes = <&rimps 1>;
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x18200000 0x10000>,
<0x18210000 0x10000>,
<0x18220000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 0>;
system_pm {
compatible = "qcom,system-pm";
};
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
rpmhcc: qcom,rpmhclk {
compatible = "qcom,yupik-rpmh-clk";
#clock-cells = <1>;
};
};
disp_rsc: rsc@af20000 {
label = "disp_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0xaf20000 0x10000>;
reg-names = "drv-0";
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0x1c00>;
qcom,drv-id = <0>;
qcom,tcs-config = <ACTIVE_TCS 0>,
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
disp_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
};
sde_rsc_rpmh {
compatible = "qcom,sde-rsc-rpmh";
cell-index = <0>;
};
};
spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0x1100>,
<0xc600000 0x2000000>,
<0xe600000 0x100000>,
<0xe700000 0xa0000>,
<0xc40a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
qcom,channel = <0>;
qcom,ee = <0>;
};
spmi_debug_bus: qcom,spmi-debug@6b12000 {
compatible = "qcom,spmi-pmic-arb-debug";
reg = <0x6b12000 0x60>, <0x7820b0 0x4>;
reg-names = "core", "fuse";
clocks = <&aopcc QDSS_CLK>;
clock-names = "core_clk";
qcom,fuse-disable-bit = <24>;
#address-cells = <2>;
#size-cells = <0>;
status = "disabled";
qcom,pmk8350-debug@0 {
compatible = "qcom,spmi-pmic";
reg = <0 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm7325-debug@1 {
compatible = "qcom,spmi-pmic";
reg = <1 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8350c-debug@2 {
compatible = "qcom,spmi-pmic";
reg = <2 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pm8350b-debug@3 {
compatible = "qcom,spmi-pmic";
reg = <3 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
qcom,pmr735a-debug@5 {
compatible = "qcom,spmi-pmic";
reg = <4 SPMI_USID>;
#address-cells = <2>;
#size-cells = <0>;
qcom,can-sleep;
};
};
qcom,pmic_glink {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
qcom,subsys-name = "adsp";
qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
battery_charger: qcom,battery_charger {
compatible = "qcom,battery-charger";
};
qcom,ucsi {
compatible = "qcom,ucsi-glink";
port {
usb_port0_connector: endpoint {
remote-endpoint = <&usb_port0>;
};
};
};
altmode: qcom,altmode {
compatible = "qcom,altmode-glink";
#altmode-cells = <1>;
};
};
qcom,pmic_glink_log {
compatible = "qcom,pmic-glink";
qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";
qcom,battery_debug {
compatible = "qcom,battery-debug";
};
spmi_glink_debug: qcom,spmi_glink_debug {
compatible = "qcom,spmi-glink-debug";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* Primary SPMI bus */
spmi@0 {
reg = <0>;
#address-cells = <2>;
#size-cells = <0>;
qcom,pm8350b-debug@3 {
compatible = "qcom,spmi-pmic";
reg = <3 SPMI_USID>;
qcom,can-sleep;
};
};
/* Secondary (QUP) SPMI bus */
spmi@1 {
reg = <1>;
#address-cells = <2>;
#size-cells = <0>;
qcom,smb1394-debug@b {
compatible = "qcom,spmi-pmic";
reg = <11 SPMI_USID>;
qcom,can-sleep;
};
qcom,smb1394-debug@c {
compatible = "qcom,spmi-pmic";
reg = <12 SPMI_USID>;
qcom,can-sleep;
};
};
};
};
thermal_zones: thermal-zones {
};
qmi_tmd: qmi-tmd-devices {
compatible = "qcom,qmi-cooling-devices";
};
tcsr_mutex_block: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_block 0 0x1000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1fc0000 {
compatible = "syscon";
reg = <0x1fc0000 0x30000>;
};
smem: qcom,smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
qcom,smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
qcom,entry-name = "rdbg";
#qcom,smem-state-cells = <1>;
};
smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
qcom,entry-name = "rdbg";
interrupt-controller;
#interrupt-cells = <2>;
};
sleepstate_smp2p_out: sleepstate-out {
qcom,entry-name = "sleepstate";
#qcom,smem-state-cells = <1>;
};
sleepstate_smp2p_in: qcom,sleepstate-in {
qcom,entry-name = "sleepstate_see";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p_sleepstate {
compatible = "qcom,smp2p-sleepstate";
qcom,smem-states = <&sleepstate_smp2p_out 0>;
interrupt-parent = <&sleepstate_smp2p_in>;
interrupts = <0 0>;
interrupt-names = "smp2p-sleepstate-in";
};
qcom,smp2p-nsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
qcom,entry-name = "rdbg";
#qcom,smem-state-cells = <1>;
};
smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
qcom,entry-name = "rdbg";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
/* ipa - inbound entry from mss */
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-wpss {
compatible = "qcom,smp2p";
qcom,smem = <617>, <616>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <13>;
wpss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
wpss_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
qcom,entry-name = "wlan";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_wlan_1_out: qcom,smp2p-wlan-1-out {
qcom,entry-name = "wlan";
#qcom,smem-state-cells = <1>;
};
};
qcom,glink {
compatible = "qcom,glink";
#address-cells = <1>;
#size-cells = <1>;
ranges;
glink_modem: modem {
qcom,remote-pid = <1>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "mpss_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,glink-label = "mpss";
qcom,modem_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,low-latency;
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,modem_ds {
qcom,glink-channels = "DS";
qcom,intents = <0x4000 0x2>;
};
qcom,modem_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_adsp>,
<&glink_wpss>;
};
};
glink_adsp: adsp {
qcom,remote-pid = <2>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "adsp_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "adsp";
qcom,glink-label = "lpass";
qcom,adsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,adsp_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_modem>,
<&glink_cdsp>,
<&glink_wpss>;
};
qcom,pmic_glink_rpmsg {
qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
};
qcom,pmic_glink_log_rpmsg {
qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
qcom,intents = <0x800 5
0xc00 3>;
};
};
glink_cdsp: cdsp {
qcom,remote-pid = <5>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "dsps_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "cdsp";
qcom,glink-label = "cdsp";
qcom,cdsp_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,cdsp_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_adsp>,
<&glink_wpss>;
};
qcom,msm_cdsprm_rpmsg {
compatible = "qcom,msm-cdsprm-rpmsg";
qcom,glink-channels = "cdsprmglink-apps-dsp";
qcom,intents = <0x20 12>;
msm_cdsp_rm: qcom,msm_cdsp_rm {
compatible = "qcom,msm-cdsp-rm";
qcom,qos-latency-us = <70>;
qcom,qos-maxhold-ms = <20>;
};
};
};
glink_wpss: wpss {
qcom,remote-pid = <13>;
transport = "smem";
mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "wpss_smem";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_WPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
label = "wpss";
qcom,glink-label = "wpss";
qcom,wpss_qrtr {
qcom,glink-channels = "IPCRTR";
qcom,intents = <0x800 5
0x2000 3
0x4400 2>;
};
qcom,wpss_glink_ssr {
qcom,glink-channels = "glink_ssr";
qcom,notify-edges = <&glink_modem>,
<&glink_adsp>,
<&glink_cdsp>;
};
};
};
qcom,glinkpkt {
compatible = "qcom,glinkpkt";
qcom,glinkpkt-at-mdm0 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DS";
qcom,glinkpkt-dev-name = "at_mdm0";
};
qcom,glinkpkt-apr-apps2 {
qcom,glinkpkt-edge = "adsp";
qcom,glinkpkt-ch-name = "apr_apps2";
qcom,glinkpkt-dev-name = "apr_apps2";
};
qcom,glinkpkt-data40-cntl {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA40_CNTL";
qcom,glinkpkt-dev-name = "smdcntl8";
};
qcom,glinkpkt-data1 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA1";
qcom,glinkpkt-dev-name = "smd7";
};
qcom,glinkpkt-data4 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA4";
qcom,glinkpkt-dev-name = "smd8";
};
qcom,glinkpkt-data11 {
qcom,glinkpkt-edge = "mpss";
qcom,glinkpkt-ch-name = "DATA11";
qcom,glinkpkt-dev-name = "smd11";
};
};
pil_wpss: qcom,wpss@8a00000 {
compatible = "qcom,pil-tz-generic";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
vdd_cx-supply = <&VDD_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
qcom,proxy-reg-names = "vdd_cx","vdd_mx";
qcom,firmware-name = "wpss";
memory-region = <&pil_wpss_mem>;
qcom,proxy-timeout-ms = <10000>;
qcom,minidump-id = <4>;
qcom,ssctl-instance-id = <0x19>;
qcom,pas-id = <0x6>;
qcom,smem-id = <626>;
qcom,signal-aop;
qcom,complete-ramdump;
qcom,ignore-ssr-failure;
/* Inputs from wpss */
interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>,
<&wpss_smp2p_in 0 0>,
<&wpss_smp2p_in 2 0>,
<&wpss_smp2p_in 1 0>,
<&wpss_smp2p_in 3 0>,
<&wpss_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack",
"qcom,shutdown-ack";
/* Outputs to wpss */
qcom,smem-states = <&wpss_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
mboxes = <&qmp_aop 0>;
mbox-names = "wpss-pil";
};
qmp_aop: qcom,qmp-aop@c300000 {
compatible = "qcom,qmp-mbox";
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
mbox-names = "aop_qmp";
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_AOP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
reg = <0xc300000 0x400>;
reg-names = "msgram";
label = "aop";
qcom,early-boot;
priority = <0>;
mbox-desc-offset = <0x0>;
#mbox-cells = <1>;
};
aop-msg-client {
compatible = "qcom,debugfs-qmp-client";
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
};
qcom-secure-buffer {
compatible = "qcom,secure-buffer";
qcom,vmid-cp-camera-preview-ro;
};
qcom-mem-buf {
compatible = "qcom,mem-buf";
qcom,mem-buf-capabilities = "supplier";
};
pil_scm_pas {
compatible = "qcom,pil-tz-scm-pas";
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
};
sdhc_1: sdhci@7C4000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>,
<0x007c8000 0x8000>, <0x7d0000 0x9000>;
reg-names = "hc_mem", "cqhci_mem", "cqhci_ice",
"cqhci_ice_hwkm";
iommus = <&apps_smmu 0xc0 0x0>;
dma-coherent;
qcom,iommu-dma = "fastmap";
qcom,iommu-dma-addr-pool = <0x40000000 0x20000000>;
qcom,iommu-geometry = <0x40000000 0x20000000>;
interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
clock-names = "core", "iface", "ice_core";
qcom,ice-clk-rates = <300000000 100000000>;
interconnects = <&aggre1_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDCC_1>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
qcom,msm-bus,name = "sdhc1";
qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
/* No Vote */
<0 0>, <0 0>,
/* 400 KB/s*/
<1000 590000>, <2000 1590000>,
/* 25 MB/s */
<50000 590000>, <30000 1590000>,
/* 50 MB/s */
<80000 590000>, <40000 1590000>,
/* 100 MB/s */
<100000 590000>, <50000 1590000>,
/* 200 MB/s */
<150000 2060000>, <80000 6440000>,
/* 400 MB/s */
<261438 2060000>, <300000 6440000>,
/* Max. bandwidth */
<1338562 4096000>, <1338562 9170000>;
qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
100000000 200000000 400000000 4294967295>;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
cap-mmc-hw-reset;
bus-width = <8>;
non-removable;
supports-cqe;
qcom,devfreq,freq-table = <50000000 200000000>;
qcom,scaling-lower-bus-speed-mode = "DDR52";
/* Add dt entry for gcc hw reset */
resets = <&gcc GCC_SDCC1_BCR>;
reset-names = "core_reset";
status = "disabled";
qos0 {
mask = <0x0f>;
vote = <61>;
};
qos1 {
mask = <0xf0>;
vote = <67>;
};
};
sdhc_2: sdhci@8804000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0x08804000 0x1000>;
reg-names = "hc_mem";
iommus = <&apps_smmu 0x100 0x0>;
dma-coherent;
qcom,iommu-dma = "bypass";
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
clock-names = "core", "iface";
bus-width = <4>;
interconnects = <&aggre1_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_SDCC_2>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
qcom,msm-bus,name = "sdhc2";
qcom,msm-bus,num-cases = <7>;
qcom,msm-bus,num-paths = <2>;
qcom,msm-bus,vectors-KBps =
/* No Vote */
<0 0>, <0 0>,
/* 400 KB/s*/
<1000 590000>, <2000 1590000>,
/* 25 MB/s */
<50000 590000>, <30000 1590000>,
/* 50 MB/s */
<80000 590000>, <40000 1590000>,
/* 100 MB/s */
<100000 590000>, <50000 1590000>,
/* 200 MB/s */
<261438 2060000>, <300000 6440000>,
/* Max. bandwidth */
<1338562 4096000>, <1338562 9170000>;
qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
100000000 200000000 4294967295>;
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
qcom,devfreq,freq-table = <50000000 202000000>;
status = "disabled";
qos0 {
mask = <0x0f>;
vote = <61>;
};
qos1 {
mask = <0xf0>;
vote = <67>;
};
};
qcom,trustedvm@d0800000 {
compatible = "qcom,pil-tz-generic";
status = "ok"
qcom,pas-id = <28>;
qcom,firmware-name = "trustedvm";
memory-region = <&pil_trustedvm_mem>;
};
qcom,guestvm_loader {
compatible = "qcom,guestvm-loader";
image_to_be_loaded = "trustedvm";
};
qcom,svm_neuron_block {
compatible = "qcom,neuron-service";
#address-cells = <1>;
#size-cells = <0>;
protocol {
compatible = "qcom,neuron-protocol-block";
processes = "server";
};
application {
compatible = "qcom,neuron-block-server";
};
channel@0 {
compatible = "qcom,neuron-channel-haven-shmem";
reg = <0>;
class = "message-queue";
direction = "receive";
max-size = <0 65536>;
shared-buffer = <&chan0_shbuf>;
qcom,primary;
haven-label = <1>;
peer-name = <2>;
};
channel@1 {
compatible = "qcom,neuron-channel-haven-shmem";
reg = <1>;
class = "message-queue";
direction = "send";
max-size = <0 65536>;
shared-buffer = <&chan1_shbuf>;
qcom,primary;
haven-label = <2>;
peer-name = <2>;
};
};
qrtr-haven {
compatible = "qcom,qrtr-haven";
qcom,master;
haven-label = <3>;
peer-name = <2>;
shared-buffer = <&qrtr_shbuf>;
};
pil_modem: qcom,mss@4080000 {
compatible = "qcom,pil-tz-generic";
reg = <0x4080000 0x100>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
vdd_mss-supply = <&VDD_MODEM_LEVEL>;
qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
qcom,proxy-reg-names = "vdd_cx", "vdd_mss";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <4>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <421>;
qcom,sysmon-id = <0>;
qcom,minidump-id = <3>;
qcom,ssctl-instance-id = <0x12>;
qcom,firmware-name = "modem";
memory-region = <&pil_mpss_mem>;
qcom,signal-aop;
qcom,complete-ramdump;
interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
/* Inputs from mss */
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<&modem_smp2p_in 0 0>,
<&modem_smp2p_in 2 0>,
<&modem_smp2p_in 1 0>,
<&modem_smp2p_in 3 0>,
<&modem_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack",
"qcom,shutdown-ack";
/* Outputs to mss */
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
mboxes = <&qmp_aop 0>;
mbox-names = "mss-pil";
};
qcom,lpass@3700000 {
compatible = "qcom,pil-tz-generic";
reg = <0x3700000 0x00100>;
vdd_cx-supply = <&VDD_LPI_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
vdd_mx-supply = <&VDD_LPI_MX_LEVEL>;
qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
qcom,proxy-reg-names = "vdd_cx","vdd_mx";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <1>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <423>;
qcom,minidump-id = <5>;
qcom,sysmon-id = <1>;
qcom,ssctl-instance-id = <0x14>;
qcom,firmware-name = "adsp";
memory-region = <&pil_adsp_mem>;
qcom,signal-aop;
qcom,complete-ramdump;
qcom,minidump-as-elf32;
/* Inputs from lpass */
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&adsp_smp2p_in 0 0>,
<&adsp_smp2p_in 2 0>,
<&adsp_smp2p_in 1 0>,
<&adsp_smp2p_in 3 0>,
<&adsp_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack",
"qcom,shutdown-ack";
/* Outputs to lpass */
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
mboxes = <&qmp_aop 0>;
mbox-names = "adsp-pil";
};
qcom,turing@a300000 {
compatible = "qcom,pil-tz-generic";
reg = <0xa300000 0x100000>;
vdd_cx-supply = <&VDD_CX_LEVEL>;
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
vdd_mx-supply = <&VDD_MX_LEVEL>;
qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
qcom,proxy-reg-names = "vdd_cx","vdd_mx";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
qcom,proxy-clock-names = "xo";
qcom,pas-id = <18>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <601>;
qcom,minidump-id = <7>;
qcom,sysmon-id = <7>;
qcom,ssctl-instance-id = <0x17>;
qcom,firmware-name = "cdsp";
memory-region = <&pil_cdsp_mem>;
qcom,signal-aop;
qcom,complete-ramdump;
qcom,minidump-as-elf32;
interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
/* Inputs from turing */
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
<&cdsp_smp2p_in 0 0>,
<&cdsp_smp2p_in 2 0>,
<&cdsp_smp2p_in 1 0>,
<&cdsp_smp2p_in 3 0>,
<&cdsp_smp2p_in 7 0>;
interrupt-names = "qcom,wdog",
"qcom,err-fatal",
"qcom,proxy-unvote",
"qcom,err-ready",
"qcom,stop-ack",
"qcom,shutdown-ack";
/* Outputs to turing */
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "qcom,force-stop";
mboxes = <&qmp_aop 0>;
mbox-names = "cdsp-pil";
};
qcom,rmtfs_sharedmem@0 {
compatible = "qcom,sharedmem-uio";
reg = <0x0 0x280000>;
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
qcom,vm-nav-path;
};
mem_dump {
compatible = "qcom,mem-dump";
memory-region = <&dump_mem>;
c0_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x0>;
};
c100_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x1>;
};
c200_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x2>;
};
c300_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x3>;
};
c400_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x4>;
};
c500_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x5>;
};
c600_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x6>;
};
c700_context {
qcom,dump-size = <0x800>;
qcom,dump-id = <0x7>;
};
c0_scandump {
qcom,dump-size = <0x10100>;
qcom,dump-id = <0x130>;
};
c100_scandump {
qcom,dump-size = <0x10100>;
qcom,dump-id = <0x131>;
};
c200_scandump {
qcom,dump-size = <0x10100>;
qcom,dump-id = <0x132>;
};
c300_scandump {
qcom,dump-size = <0x10100>;
qcom,dump-id = <0x133>;
};
c400_scandump {
qcom,dump-size = <0x40000>;
qcom,dump-id = <0x134>;
};
c500_scandump {
qcom,dump-size = <0x40000>;
qcom,dump-id = <0x135>;
};
c600_scandump {
qcom,dump-size = <0x40000>;
qcom,dump-id = <0x136>;
};
c700_scandump {
qcom,dump-size = <0x40000>;
qcom,dump-id = <0x137>;
};
cpuss_reg {
qcom,dump-size = <0x30000>;
qcom,dump-id = <0xef>;
};
l1_icache0 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x60>;
};
l1_icache100 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x61>;
};
l1_icache200 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x62>;
};
l1_icache300 {
qcom,dump-size = <0x10900>;
qcom,dump-id = <0x63>;
};
l1_icache400 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x64>;
};
l1_icache500 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x65>;
};
l1_icache600 {
qcom,dump-size = <0x15100>;
qcom,dump-id = <0x66>;
};
l1_icache700 {
qcom,dump-size = <0x32100>;
qcom,dump-id = <0x67>;
};
l1_dcache0 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x80>;
};
l1_dcache100 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x81>;
};
l1_dcache200 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x82>;
};
l1_dcache300 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x83>;
};
l1_dcache400 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x84>;
};
l1_dcache500 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x85>;
};
l1_dcache600 {
qcom,dump-size = <0x9100>;
qcom,dump-id = <0x86>;
};
l1_dcache700 {
qcom,dump-size = <0x12100>;
qcom,dump-id = <0x87>;
};
l1_itlb400 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x24>;
};
l1_itlb500 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x25>;
};
l1_itlb600 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x26>;
};
l1_itlb700 {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x27>;
};
l1_dtlb400 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x44>;
};
l1_dtlb500 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x45>;
};
l1_dtlb600 {
qcom,dump-size = <0x300>;
qcom,dump-id = <0x46>;
};
l1_dtlb700 {
qcom,dump-size = <0x3a0>;
qcom,dump-id = <0x47>;
};
l2_cache400 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc4>;
};
l2_cache500 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc5>;
};
l2_cache600 {
qcom,dump-size = <0x90100>;
qcom,dump-id = <0xc6>;
};
l2_cache700 {
qcom,dump-size = <0x120100>;
qcom,dump-id = <0xc7>;
};
l2_tlb0 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x120>;
};
l2_tlb100 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x121>;
};
l2_tlb200 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x122>;
};
l2_tlb300 {
qcom,dump-size = <0x5b00>;
qcom,dump-id = <0x123>;
};
l2_tlb400 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x124>;
};
l2_tlb500 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x125>;
};
l2_tlb600 {
qcom,dump-size = <0x6100>;
qcom,dump-id = <0x126>;
};
l2_tlb700 {
qcom,dump-size = <0xc100>;
qcom,dump-id = <0x127>;
};
gemnoc {
qcom,dump-size = <0x100000>;
qcom,dump-id = <0x162>;
};
mhm_scan {
qcom,dump-size = <0x20000>;
qcom,dump-id = <0x161>;
};
rpmh {
qcom,dump-size = <0x2000000>;
qcom,dump-id = <0xec>;
};
rpm_sw {
qcom,dump-size = <0x28000>;
qcom,dump-id = <0xea>;
};
pmic {
qcom,dump-size = <0x200000>;
qcom,dump-id = <0xe4>;
};
fcm {
qcom,dump-size = <0x8400>;
qcom,dump-id = <0xee>;
};
etf_swao {
qcom,dump-size = <0x10000>;
qcom,dump-id = <0xf1>;
};
etr_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x100>;
};
etfswao_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x102>;
};
LLCC_1: llcc_1_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x140>;
};
LLCC_2: llcc_2_dcache {
qcom,dump-size = <0x1141c0>;
qcom,dump-id = <0x141>;
};
misc_data {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0xe8>;
};
etf_lpass {
qcom,dump-size = <0x4000>;
qcom,dump-id = <0xf4>;
};
etflpass_reg {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x104>;
};
osm_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x163>;
};
pcu_reg {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x164>;
};
fsm_data {
qcom,dump-size = <0x400>;
qcom,dump-id = <0x165>;
};
};
qfprom: qfprom@780000 {
compatible = "qcom,qfprom";
reg = <0x780000 0x7000>;
#address-cells = <1>;
#size-cells = <1>;
read-only;
ranges;
gpu_speed_bin: gpu_speed_bin@1e9 {
reg = <0x1e9 0x2>;
bits = <5 8>;
};
gpu_gaming_bin: gpu_gaming_bin@1f5 {
reg = <0x1f5 0x1>;
bits = <5 1>;
};
gpu_model_bin: gpu_model_bin@1e9 {
reg = <0x1e9 0x2>;
bits = <5 8>;
};
feat_conf_m7: feat_conf_m7@6020 {
reg = <0x6020 0x4>;
};
feat_conf_m9: feat_conf_m9@6028 {
reg = <0x6028 0x4>;
};
adsp_variant: adsp_variant@6020 {
reg = <0x6022 0x1>;
bits = <2 4>;
};
};
qfprom_sys: qfprom@0 {
compatible = "qcom,qfprom-sys";
nvmem-cells = <&feat_conf_m7>,
<&feat_conf_m9>;
nvmem-cell-names = "feat_conf_m7",
"feat_conf_m9";
};
qcom,msm-cdsp-loader {
compatible = "qcom,cdsp-loader";
qcom,proc-img-to-load = "cdsp";
};
qcom,msm-adsprpc-mem {
compatible = "qcom,msm-adsprpc-mem-region";
memory-region = <&adsp_mem>;
restrict-access;
};
msm_fastrpc: qcom,msm_fastrpc {
compatible = "qcom,msm-fastrpc-compute";
qcom,adsp-remoteheap-vmid = <22 37>;
qcom,fastrpc-adsp-audio-pdr;
qcom,fastrpc-adsp-sensors-pdr;
qcom,rpc-latency-us = <235>;
qcom,fastrpc-gids = <2908>;
qcom,qos-cores = <0 1 2 3>;
qcom,msm_fastrpc_compute_cb1 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x11A1 0x0420>,
<&apps_smmu 0x1181 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb2 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x11A2 0x0420>,
<&apps_smmu 0x1182 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb3 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x11A3 0x0420>,
<&apps_smmu 0x1183 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb4 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x11A4 0x0420>,
<&apps_smmu 0x1184 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb5 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x11A5 0x0420>,
<&apps_smmu 0x1185 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb6 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x11A6 0x0420>,
<&apps_smmu 0x1186 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb7 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x11A7 0x0420>,
<&apps_smmu 0x1187 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb8 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x11A8 0x0420>,
<&apps_smmu 0x1188 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb9 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
qcom,secure-context-bank;
iommus = <&apps_smmu 0x11A9 0x0420>,
<&apps_smmu 0x1189 0x0420>;
qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb10 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&apps_smmu 0x1803 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb11 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&apps_smmu 0x1804 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb12 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "adsprpc-smd";
iommus = <&apps_smmu 0x1805 0x0>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
shared-cb = <5>;
};
qcom,msm_fastrpc_compute_cb13 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x11AB 0x0420>,
<&apps_smmu 0x118B 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb14 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x11AC 0x0420>,
<&apps_smmu 0x118C 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb15 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x11AD 0x0420>,
<&apps_smmu 0x118D 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
qcom,msm_fastrpc_compute_cb16 {
compatible = "qcom,msm-fastrpc-compute-cb";
label = "cdsprpc-smd";
iommus = <&apps_smmu 0x11AE 0x0420>,
<&apps_smmu 0x118E 0x0420>;
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
qcom,iommu-faults = "stall-disable" , "HUPCF";
dma-coherent-hint-cached;
};
};
qcom,msm_gsi {
compatible = "qcom,msm_gsi";
};
qcom,rmnet-ipa {
compatible = "qcom,rmnet-ipa3";
qcom,rmnet-ipa-ssr;
qcom,ipa-platform-type-msm;
qcom,ipa-advertise-sg-support;
qcom,ipa-napi-enable;
};
qcom,ipa_fws {
compatible = "qcom,pil-tz-generic";
qcom,pas-id = <0xf>;
qcom,firmware-name = "yupik_ipa_fws";
qcom,pil-force-shutdown;
qcom,proxy-timeout-ms = <1000>;
memory-region = <&pil_ipa_gsi_mem>;
};
ipa_hw: qcom,ipa@1e00000 {
compatible = "qcom,ipa";
mboxes = <&qmp_aop 0>;
reg =
<0x1e00000 0x84000>,
<0x1e04000 0x23000>;
reg-names = "ipa-base", "gsi-base";
interrupts =
<0 654 IRQ_TYPE_LEVEL_HIGH>,
<0 432 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ipa-irq", "gsi-irq";
qcom,ipa-hw-ver = <20>; /* IPA core version = IPAv4.11 */
qcom,ipa-hw-mode = <0>;
qcom,platform-type = <1>; /* MSM platform */
qcom,ee = <0>;
qcom,use-ipa-tethering-bridge;
qcom,modem-cfg-emb-pipe-flt;
qcom,ipa-wdi3-over-gsi;
qcom,arm-smmu;
qcom,smmu-fast-map;
qcom,use-64-bit-dma-mask;
qcom,ipa-endp-delay-wa-v2;
qcom,eth-bridging-not-supported;
qcom,bw-monitor-supported;
qcom,lan-rx-napi;
qcom,tx-napi;
qcom,wan-use-skb-page;
qcom,rmnet-ctl-enable;
qcom,use-gsi-ipa-fw = "yupik_ipa_fws";
qcom,tx-wrapper-cache-max-size = <400>;
qcom,ipa-gpi-event-rp-ddr;
clock-names = "core_clk";
clocks = <&rpmhcc RPMH_IPA_CLK>;
qcom,interconnect,num-cases = <5>;
qcom,interconnect,num-paths = <3>;
interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_IPA_CFG>;
interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
/* No vote */
qcom,no-vote =
<0 0 0 0 0 0>;
/* SVS2 */
qcom,svs2 =
<150000 600000 150000 1804000 0 74000>;
/* SVS */
qcom,svs =
<625000 1200000 625000 3072000 0 150000>;
/* NOMINAL */
qcom,nominal =
<1250000 2400000 1250000 6220800 0 400000>;
/* TURBO */
qcom,turbo =
<2000000 3500000 2000000 7219200 0 400000>;
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
"TURBO";
qcom,throughput-threshold = <600 2500 5000>;
qcom,scaling-exceptions = <>;
/* smp2p information */
qcom,smp2p_map_ipa_1_out {
compatible = "qcom,smp2p-map-ipa-1-out";
qcom,smem-states = <&smp2p_ipa_1_out 0>;
qcom,smem-state-names = "ipa-smp2p-out";
};
qcom,smp2p_map_ipa_1_in {
compatible = "qcom,smp2p-map-ipa-1-in";
interrupts-extended = <&smp2p_ipa_1_in 0 0>;
interrupt-names = "ipa-smp2p-in";
};
ipa_smmu_ap: ipa_smmu_ap {
compatible = "qcom,ipa-smmu-ap-cb";
iommus = <&apps_smmu 0x480 0x0>;
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
qcom,additional-mapping =
/* modem tables in IMEM */
<0x146A8000 0x146A8000 0x2000>;
dma-coherent;
qcom,iommu-dma = "fastmap";
qcom,ipa-q6-smem-size = <36864>;
};
ipa_smmu_wlan: ipa_smmu_wlan {
compatible = "qcom,ipa-smmu-wlan-cb";
iommus = <&apps_smmu 0x481 0x0>;
qcom,iommu-dma = "atomic";
dma-coherent;
};
ipa_smmu_uc: ipa_smmu_uc {
compatible = "qcom,ipa-smmu-uc-cb";
iommus = <&apps_smmu 0x482 0x0>;
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
qcom,iommu-dma = "atomic";
};
ipa_smmu_11ad: ipa_smmu_11ad {
compatible = "qcom,ipa-smmu-11ad-cb";
iommus = <&apps_smmu 0x483 0x0>;
dma-coherent;
qcom,shared-cb;
qcom,iommu-group = <>;
};
};
qcom,sps {
compatible = "qcom,msm-sps-4k";
qcom,pipe-attr-ee;
};
};
#include "shima-gdsc.dtsi"
#include "yupik-coresight.dtsi"
#include "yupik-pinctrl.dtsi"
#include "yupik-pm.dtsi"
#include "ipcc-test-yupik.dtsi"
#include "yupik-regulators.dtsi"
#include "display/yupik-sde.dtsi"
#include "yupik-pcie.dtsi"
&gcc_ufs_phy_gdsc {
qcom,support-hw-trigger;
status = "ok"
};
&gcc_usb30_prim_gdsc {
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
status = "ok"
};
&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
status = "ok"
};
&hlos1_vote_turing_mmu_tbu0_gdsc {
status = "ok"
};
&hlos1_vote_turing_mmu_tbu1_gdsc {
status = "ok"
};
&cam_cc_titan_top_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
reg = <0xad0c194 0x4>;
status = "ok"
};
&cam_cc_bps_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,support-hw-trigger;
status = "ok"
};
&cam_cc_ife_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok"
};
&cam_cc_ife_1_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok"
};
&cam_cc_ife_2_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok"
};
&cam_cc_ipe_0_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,support-hw-trigger;
status = "ok"
};
&disp_cc_mdss_core_gdsc {
reg = <0xaf01004 0x4>;
clocks = <&gcc GCC_DISP_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,support-hw-trigger;
status = "ok"
};
&gpu_cx_gdsc {
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,retain-regs;
status = "ok"
};
&gpu_gx_gdsc {
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_GFX_LEVEL>;
qcom,retain-regs;
qcom,skip-disable-before-sw-enable;
status = "ok"
};
&video_cc_mvs0_gdsc {
reg = <0xaaf3004 0x4>;
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
qcom,support-hw-trigger;
status = "ok"
};
&video_cc_mvsc_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok"
};
#include "yupik-vidc.dtsi"
#include "yupik-usb.dtsi"
#include "yupik-ion.dtsi"
#include "msm-arm-smmu-yupik.dtsi"
#include "yupik-qupv3.dtsi"
#include "yupik-audio.dtsi"
#include "camera/yupik-camera.dtsi"
#include "msm-rdbg.dtsi"
#include "yupik-gpu.dtsi"
#include "yupik-thermal.dtsi"
/* HS UART */
&qupv3_se7_4uart {
status = "ok"
};
&qupv3_se1_i2c {
status = "ok"
nq@64 {
compatible = "rtc6226";
reg = <0x64>;
fmint-gpio = <&tlmm 18 0>;
vdd-supply = <&L11C>;
rtc6226,vdd-supply-voltage = <2800000 2800000>;
rtc6226,vdd-load = <15000>;
vio-supply = <&L19B>;
rtc6226,vio-supply-voltage = <1800000 1800000>;
};
};
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