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https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
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| Filename | Latest commit message | Latest commit date |
|---|---|---|
7f6d2188ec
commit 44b3834b2eed595af07021b1c64e6f9bc396398b upstream. Cortex-A57 and Cortex-A72 have an erratum where an interrupt that occurs between a pair of AES instructions in aarch32 mode may corrupt the ELR. The task will subsequently produce the wrong AES result. The AES instructions are part of the cryptographic extensions, which are optional. User-space software will detect the support for these instructions from the hwcaps. If the platform doesn't support these instructions a software implementation should be used. Remove the hwcap bits on affected parts to indicate user-space should not use the AES instructions. Acked-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: James Morse <james.morse@arm.com> Link: https://lore.kernel.org/r/20220714161523.279570-3-james.morse@arm.com Signed-off-by: Will Deacon <will@kernel.org> [florian: resolved conflicts in arch/arm64/tools/cpucaps and cpu_errata.c] Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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| .. | ||
| acpi_object_usage.rst | ||
| arm-acpi.rst | ||
| booting.rst | ||
| cpu-feature-registers.rst | ||
| elf_hwcaps.rst | ||
| hugetlbpage.rst | ||
| index.rst | ||
| kasan-offsets.sh | ||
| legacy_instructions.rst | ||
| memory.rst | ||
| perf.txt | ||
| pointer-authentication.rst | ||
| silicon-errata.rst | ||
| sve.rst | ||
| tagged-address-abi.rst | ||
| tagged-pointers.rst | ||