Thomas Bogendoerfer
14defd90f5
[MIPS] Fix 32bit kernels on R4k with 128 byte cache line size ...
The generated copy_page for R4k CPU with a 128 byte cache line size used
Create Dirty Exclusive cache line operations even if only part of the
cache line was filled. This change avoids generating cache operations,
if only part of the cache line size is copied in one loop. It also
increases the maxmimum loop size, because the generated code even fits
into the available space for r4k CPUs with 128 byte cache line size.
Signed-off-by: Thomas Bogendoerfer <[email protected] >
Signed-off-by: Ralf Baechle <[email protected] >
2008-07-08 19:33:46 +01:00
[MIPS] Au1200: MMC resource size off by one
2008-06-16 15:14:49 +01:00
basler /excite
proc: switch /proc/excite/unit_id to seq_file interface
2008-04-29 08:06:19 -07:00
[MIPS] TANBAC: Update defconfig
2008-06-16 15:14:49 +01:00
[MIPS] markeins: build fix
2008-05-12 16:46:56 +01:00
[MIPS] Add RM200 with R5000 CPU to known ARC machines
2008-06-16 15:14:46 +01:00
gt64120 /wrppmc
[MIPS] cevt-txx9: Reset timer counter on initialization
2008-07-03 19:14:27 +01:00
[MIPS] Lasat: sysctl fixup
2008-06-16 15:14:48 +01:00
lemote /lm2e
[MIPS] Malta: Always compile MTD platform device registration code.
2008-06-16 15:14:48 +01:00
[MIPS] Fix 32bit kernels on R4k with 128 byte cache line size
2008-07-08 19:33:46 +01:00
nxp /pnx8550
[MIPS] Fix build for PNX platforms.
2008-06-16 15:14:47 +01:00
[MIPS] Fix build failure in mips oprofile code
2008-05-12 16:46:56 +01:00
[MIPS] Vr41xx: Initialize PCI io_map_base
2008-06-16 15:14:48 +01:00
[MIPS] msp_hwbutton.c: minor irq handler cleanups
2008-05-12 16:46:52 +01:00
[MIPS] IP27: misc fixes
2008-06-05 18:13:15 +01:00
[MIPS] IP32: Fix unexpected irq 71
2008-07-03 19:14:27 +01:00
[MIPS] Sibyte: Build RTC support as an object
2008-06-16 15:14:47 +01:00
[MIPS] IP22: Fix crashes due to wrong L1_CACHE_BYTES
2008-07-03 19:14:27 +01:00
[MIPS] Sibyte: Build RTC support as an object
2008-06-16 15:14:47 +01:00
14defd90f5