mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 10:41:38 -04:00
3c44286a6e
A new LUTDMA instance is added to the DMA hardware in Lahaina. This change updates the corresponding entries, including block size, offsets, and version. The DSPP IGC and Gamut versions have been updated to indicate new HW programming changes using SB LUTDMA. Change-Id: I44091e99d4a47162faf539eeb2e64f3799dc8855
620 lines
18 KiB
Devicetree
620 lines
18 KiB
Devicetree
#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
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&soc {
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mdss_mdp: qcom,mdss_mdp@ae00000 {
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compatible = "qcom,sde-kms";
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reg = <0x0ae00000 0x84000>,
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<0x0aeb0000 0x2008>,
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<0x0aeac000 0x800>,
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<0x0af50000 0x038>;
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reg-names = "mdp_phys",
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"vbif_phys",
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"regdma_phys",
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"swfuse_phys";
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clocks =
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<&clock_gcc GCC_DISP_AHB_CLK>,
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<&clock_gcc GCC_DISP_HF_AXI_CLK>,
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<&clock_gcc GCC_DISP_SF_AXI_CLK>,
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<&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
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<&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
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<&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>,
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<&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
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clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
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"iface_clk", "core_clk", "vsync_clk",
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"lut_clk", "rot_clk";
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clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>;
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clock-max-rate = <0 0 0 0 460000000 19200000 460000000
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460000000>;
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mmcx-supply = <&VDD_MMCX_LEVEL>;
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vdd-supply = <&disp_cc_mdss_core_gdsc>;
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/* interrupt config */
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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/* hw blocks */
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qcom,sde-off = <0x1000>;
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qcom,sde-len = <0x494>;
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qcom,sde-ctl-off = <0x16000 0x17000 0x18000
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0x19000 0x1a000 0x1b000>;
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qcom,sde-ctl-size = <0x1e8>;
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qcom,sde-ctl-display-pref = "primary", "none", "none",
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"none", "none", "none";
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qcom,sde-mixer-off = <0x45000 0x46000 0x47000
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0x48000 0x49000 0x4a000>;
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qcom,sde-mixer-size = <0x320>;
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qcom,sde-mixer-display-pref = "primary", "primary", "none",
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"none", "none", "none";
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qcom,sde-mixer-cwb-pref = "none", "none", "cwb",
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"cwb", "cwb", "cwb";
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qcom,sde-dspp-top-off = <0x1300>;
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qcom,sde-dspp-top-size = <0x80>;
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qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
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qcom,sde-dspp-size = <0x1800>;
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qcom,sde-dspp-rc-version = <0x00010000>;
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qcom,sde-dspp-rc-off = <0x15800 0x14c00>;
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qcom,sde-dspp-rc-size = <0x100>;
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qcom,sde-dspp-rc-mem-size = <2720>;
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qcom,sde-dest-scaler-top-off = <0x00061000>;
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qcom,sde-dest-scaler-top-size = <0x1c>;
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qcom,sde-dest-scaler-off = <0x800 0x1000>;
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qcom,sde-dest-scaler-size = <0x800>;
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qcom,sde-wb-off = <0x66000>;
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qcom,sde-wb-size = <0x2c8>;
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qcom,sde-wb-xin-id = <6>;
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qcom,sde-wb-id = <2>;
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qcom,sde-wb-clk-ctrl = <0x2bc 16>;
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qcom,sde-intf-off = <0x35000 0x36000
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0x37000 0x38000>;
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qcom,sde-intf-size = <0x2c0>;
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qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
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qcom,sde-intf-tear-irq-off = <0 0x36800 0x37800 0>;
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qcom,sde-pp-off = <0x6a000 0x6b000
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0x6c000 0x6d000 0x6e000 0x6f000>;
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qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>;
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qcom,sde-pp-size = <0xd4>;
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qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>;
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qcom,sde-merge-3d-off = <0x4f000 0x50000 0x51000>;
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qcom,sde-merge-3d-size = <0x10>;
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qcom,sde-cdm-off = <0x7a200>;
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qcom,sde-cdm-size = <0x224>;
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qcom,sde-dsc-off = <0x81000 0x81000 0x82000 0x82000>;
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qcom,sde-dsc-size = <0x140>;
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qcom,sde-dsc-pair-mask = <2 1 4 3>;
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qcom,sde-dsc-hw-rev = "dsc_1_2";
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qcom,sde-dsc-enc = <0x100 0x200 0x100 0x200>;
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qcom,sde-dsc-ctl = <0xF00 0xF80 0xF00 0xF80>;
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qcom,sde-dsc-native422-supp = <0 0 1 1>;
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qcom,sde-dither-off = <0xe0 0xe0 0xe0
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0xe0 0xe0 0xe0>;
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qcom,sde-dither-version = <0x00020000>;
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qcom,sde-dither-size = <0x20>;
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qcom,sde-vdc-off = <0x7C000>;
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qcom,sde-vdc-size = <0xf10>;
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qcom,sde-vdc-hw-rev = "vdc_1_1";
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qcom,sde-vdc-enc = <0x200>;
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qcom,sde-vdc-ctl = <0xf00>;
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qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
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"dma", "dma", "dma", "dma";
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qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
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0x25000 0x27000 0x29000 0x2b000>;
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qcom,sde-sspp-src-size = <0x1f8>;
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qcom,sde-sspp-xin-id = <0 4 8 12
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1 5 9 13>;
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qcom,sde-sspp-excl-rect = <1 1 1 1
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1 1 1 1>;
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qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
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qcom,sde-smart-dma-rev = "smart_dma_v2p5";
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qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>;
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qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
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0xb0 0xc8 0xe0 0xf8 0x110>;
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qcom,sde-max-per-pipe-bw-kbps = <3900000 3900000
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3900000 3900000
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3900000 3900000
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3900000 3900000>;
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qcom,sde-max-per-pipe-bw-high-kbps = <5200000 5200000
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5200000 5200000
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5200000 5200000
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5200000 5200000>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-sspp-clk-ctrl =
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<0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
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<0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
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qcom,sde-sspp-csc-off = <0x1a00>;
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qcom,sde-csc-type = "csc-10bit";
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qcom,sde-qseed-type = "qseedv3lite";
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qcom,sde-sspp-qseed-off = <0xa00>;
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qcom,sde-mixer-linewidth = <2560>;
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qcom,sde-sspp-linewidth = <4096>;
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qcom,sde-wb-linewidth = <4096>;
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qcom,sde-mixer-blendstages = <0xb>;
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qcom,sde-highest-bank-bit = <0x3>;
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qcom,sde-ubwc-version = <0x400>;
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qcom,sde-ubwc-swizzle = <0x6>;
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qcom,sde-ubwc-bw-calc-version = <0x1>;
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qcom,sde-ubwc-static = <0x1>;
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qcom,sde-macrotile-mode = <0x1>;
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qcom,sde-smart-panel-align-mode = <0xc>;
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qcom,sde-panic-per-pipe;
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qcom,sde-has-cdp;
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qcom,sde-has-src-split;
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qcom,sde-pipe-order-version = <0x1>;
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qcom,sde-has-dim-layer;
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qcom,sde-has-dest-scaler;
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qcom,sde-has-idle-pc;
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qcom,sde-max-dest-scaler-input-linewidth = <2048>;
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qcom,sde-max-dest-scaler-output-linewidth = <2560>;
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qcom,sde-max-bw-low-kbps = <11800000>;
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qcom,sde-max-bw-high-kbps = <15500000>;
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qcom,sde-min-core-ib-kbps = <2500000>;
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qcom,sde-min-llcc-ib-kbps = <0>;
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qcom,sde-min-dram-ib-kbps = <800000>;
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qcom,sde-dram-channels = <2>;
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qcom,sde-num-nrt-paths = <0>;
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qcom,sde-dspp-ltm-version = <0x00010000>;
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/* offsets are based off dspp 0 and dspp 1 */
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qcom,sde-dspp-ltm-off = <0x15300 0x14300>;
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qcom,sde-uidle-off = <0x80000>;
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qcom,sde-uidle-size = <0x70>;
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qcom,sde-vbif-off = <0>;
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qcom,sde-vbif-size = <0x1040>;
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qcom,sde-vbif-id = <0>;
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qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
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qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
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qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
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qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
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qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
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qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 6>;
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qcom,sde-danger-lut = <0x0000ffff 0x0000ffff 0x00000000
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0x00000000 0x0000ffff 0x0000ffff>, <0x0003ffff
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0x0003ffff 0x00000000 0x00000000 0x0003ffff 0x0003ffff>;
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qcom,sde-safe-lut = <0xfff0 0xff00 0xffff 0x3ff 0xff00 0xff00>,
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<0xfe00 0xfe00 0xffff 0x3ff 0xfe00 0xfe00>;
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qcom,sde-qos-lut-linear = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
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qcom,sde-qos-lut-macrotile = <0x00112233 0x44556677>, <0x00112234 0x45566777>;
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qcom,sde-qos-lut-macrotile-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
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qcom,sde-qos-lut-linear-qseed = <0x00112233 0x66777777>, <0x00112236 0x67777777>;
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qcom,sde-qos-lut-nrt = <0x0 0x0>, <0x0 0x0>;
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qcom,sde-qos-lut-cwb = <0x66666541 0x0>, <0x66666541 0x0>;
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qcom,sde-qos-refresh-rates = <60 120>;
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qcom,sde-cdp-setting = <1 1>, <1 0>;
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qcom,sde-qos-cpu-mask = <0x3>;
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qcom,sde-qos-cpu-dma-latency = <300>;
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-reg-dma-off = <0 0x400>;
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qcom,sde-reg-dma-id = <0 1>;
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qcom,sde-reg-dma-version = <0x00020000>;
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qcom,sde-reg-dma-trigger-off = <0x119c>;
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qcom,sde-reg-dma-xin-id = <7>;
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qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
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qcom,sde-secure-sid-mask = <0x4000821>;
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/* data and reg bus scale settings */
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interconnects =
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<&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>,
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<&mmss_noc MASTER_MDP1 &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_DISPLAY_CFG>;
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interconnect-names = "qcom,sde-data-bus0", "qcom,sde-data-bus1",
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"qcom,sde-reg-bus";
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qcom,sde-sspp-vig-blocks {
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qcom,sde-vig-csc-off = <0x1a00>;
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qcom,sde-vig-qseed-off = <0xa00>;
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qcom,sde-vig-qseed-size = <0xa0>;
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qcom,sde-vig-gamut = <0x1d00 0x00060000>;
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qcom,sde-vig-igc = <0x1d00 0x00060000>;
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qcom,sde-vig-inverse-pma;
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};
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qcom,sde-sspp-dma-blocks {
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dgm@0 {
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qcom,sde-dma-igc = <0x400 0x00050000>;
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qcom,sde-dma-gc = <0x600 0x00050000>;
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qcom,sde-dma-inverse-pma;
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qcom,sde-dma-csc-off = <0x200>;
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};
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dgm@1 {
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qcom,sde-dma-igc = <0x1400 0x00050000>;
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qcom,sde-dma-gc = <0x600 0x00050000>;
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qcom,sde-dma-inverse-pma;
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qcom,sde-dma-csc-off = <0x1200>;
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};
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};
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qcom,sde-dspp-blocks {
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qcom,sde-dspp-igc = <0x1260 0x00030002>;
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qcom,sde-dspp-hsic = <0x800 0x00010007>;
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qcom,sde-dspp-memcolor = <0x880 0x00010007>;
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qcom,sde-dspp-hist = <0x800 0x00010007>;
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qcom,sde-dspp-sixzone= <0x900 0x00010007>;
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qcom,sde-dspp-vlut = <0xa00 0x00010008>;
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qcom,sde-dspp-gamut = <0x1000 0x00040003>;
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qcom,sde-dspp-pcc = <0x1700 0x00040000>;
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qcom,sde-dspp-gc = <0x17c0 0x00010008>;
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qcom,sde-dspp-dither = <0x82c 0x00010007>;
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};
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qcom,platform-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,platform-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "mmcx";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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qcom,platform-supply-entry@1 {
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reg = <0>;
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qcom,supply-name = "vdd";
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qcom,supply-min-voltage = <0>;
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qcom,supply-max-voltage = <0>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
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compatible = "qcom,smmu_sde_unsec";
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iommus = <&apps_smmu 0x820 0x402>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-earlymap; /* for cont-splash */
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};
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smmu_sde_sec: qcom,smmu_sde_sec_cb {
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compatible = "qcom,smmu_sde_sec";
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iommus = <&apps_smmu 0x821 0x400>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xa>;
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};
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};
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sde_dp: qcom,dp_display@ae90000 {
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cell-index = <0>;
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compatible = "qcom,dp-display";
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status = "disabled";
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reg = <0xae90000 0x0dc>,
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<0xae90200 0x0c0>,
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<0xae90400 0x508>,
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<0xae91000 0x094>,
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<0x88eaa00 0x200>,
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<0x88ea200 0x200>,
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<0x88ea600 0x200>,
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<0xaf02000 0x1a0>,
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<0x88ea040 0x10>,
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<0x88e8000 0x20>,
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<0x0aee1000 0x034>,
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<0xae91400 0x094>;
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/* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */
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reg-names = "dp_ahb", "dp_aux", "dp_link",
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"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
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"dp_mmss_cc", "dp_pll",
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"usb3_dp_com", "hdcp_physical", "dp_p1";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <12 0>;
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clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
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<&clock_rpmh RPMH_CXO_CLK>,
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<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
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<&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
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clock-names = "core_aux_clk", "core_usb_ref_clk_src",
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"core_usb_pipe_clk", "link_clk", "link_iface_clk",
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"pixel_clk_rcg", "pixel1_clk_rcg",
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"strm0_pixel_clk", "strm1_pixel_clk";
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qcom,phy-version = <0x420>;
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qcom,aux-cfg0-settings = [20 00];
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qcom,aux-cfg1-settings = [24 13];
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qcom,aux-cfg2-settings = [28 A4];
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qcom,aux-cfg3-settings = [2c 00];
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qcom,aux-cfg4-settings = [30 0a];
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qcom,aux-cfg5-settings = [34 26];
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qcom,aux-cfg6-settings = [38 0a];
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qcom,aux-cfg7-settings = [3c 03];
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qcom,aux-cfg8-settings = [40 b7];
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qcom,aux-cfg9-settings = [44 03];
|
|
|
|
qcom,max-pclk-frequency-khz = <675000>;
|
|
|
|
qcom,mst-enable;
|
|
qcom,widebus-enable;
|
|
qcom,dsc-feature-enable;
|
|
qcom,fec-feature-enable;
|
|
qcom,max-dp-dsc-blks = <2>;
|
|
qcom,max-dp-dsc-input-width-pixs = <2048>;
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1200000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <33000>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <912000>;
|
|
qcom,supply-max-voltage = <912000>;
|
|
qcom,supply-enable-load = <126000>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0>;
|
|
qcom,supply-max-voltage = <0>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sde_rscc: qcom,sde_rscc@af20000 {
|
|
cell-index = <0>;
|
|
compatible = "qcom,sde-rsc";
|
|
status = "disabled";
|
|
reg = <0xaf20000 0x3c50>,
|
|
<0xaf30000 0x3fd4>;
|
|
reg-names = "drv", "wrapper";
|
|
qcom,sde-rsc-version = <3>;
|
|
|
|
qcom,sde-dram-channels = <2>;
|
|
|
|
vdd-supply = <&disp_cc_mdss_core_gdsc>;
|
|
clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
|
|
clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
|
|
interconnects =
|
|
<&gem_noc MASTER_APPSS_PROC
|
|
&config_noc SLAVE_DISPLAY_CFG>;
|
|
interconnect-names = "qcom,sde-reg-bus";
|
|
};
|
|
|
|
mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
|
|
compatible = "qcom,dsi-ctrl-hw-v2.5";
|
|
label = "dsi-ctrl-0";
|
|
cell-index = <0>;
|
|
frame-threshold-time-us = <800>;
|
|
reg = <0xae94000 0x400>,
|
|
<0xaf08000 0x4>;
|
|
reg-names = "dsi_ctrl", "disp_cc_base";
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <4 0>;
|
|
vdda-1p2-supply = <&L6B>;
|
|
refgen-supply = <&refgen>;
|
|
clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
|
<&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
|
<&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
|
|
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
|
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
|
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1200000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <8350>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0>;
|
|
qcom,supply-max-voltage = <0>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
|
|
compatible = "qcom,dsi-ctrl-hw-v2.5";
|
|
label = "dsi-ctrl-1";
|
|
cell-index = <1>;
|
|
frame-threshold-time-us = <800>;
|
|
reg = <0xae96000 0x400>,
|
|
<0xaf08000 0x4>;
|
|
reg-names = "dsi_ctrl", "disp_cc_base";
|
|
interrupt-parent = <&mdss_mdp>;
|
|
interrupts = <5 0>;
|
|
vdda-1p2-supply = <&L6B>;
|
|
refgen-supply = <&refgen>;
|
|
clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
|
<&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
|
|
<&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
|
|
<&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
|
|
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
|
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
|
qcom,ctrl-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,ctrl-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-1p2";
|
|
qcom,supply-min-voltage = <1200000>;
|
|
qcom,supply-max-voltage = <1200000>;
|
|
qcom,supply-enable-load = <8350>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
|
|
qcom,core-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
qcom,core-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "refgen";
|
|
qcom,supply-min-voltage = <0>;
|
|
qcom,supply-max-voltage = <0>;
|
|
qcom,supply-enable-load = <0>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 {
|
|
compatible = "qcom,dsi-phy-v4.2";
|
|
label = "dsi-phy-0";
|
|
cell-index = <0>;
|
|
#clock-cells = <1>;
|
|
reg = <0xae94400 0x800>,
|
|
<0xae94900 0x27c>,
|
|
<0xaf03000 0x8>,
|
|
<0xae94200 0x100>;
|
|
reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";
|
|
pll-label = "dsi_pll_5nm";
|
|
vdda-0p9-supply = <&L5B>;
|
|
qcom,dsi-pll-ssc-en;
|
|
qcom,dsi-pll-ssc-mode = "down-spread";
|
|
qcom,platform-strength-ctrl = [55 03
|
|
55 03
|
|
55 03
|
|
55 03
|
|
55 00];
|
|
qcom,platform-lane-config = [00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 8a 8a];
|
|
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <880000>;
|
|
qcom,supply-enable-load = <37550>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96900 {
|
|
compatible = "qcom,dsi-phy-v4.2";
|
|
label = "dsi-phy-1";
|
|
cell-index = <1>;
|
|
#clock-cells = <1>;
|
|
reg = <0xae96400 0x800>,
|
|
<0xae96900 0x27c>,
|
|
<0xaf03000 0x8>,
|
|
<0xae96200 0x100>;
|
|
reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base";
|
|
pll-label = "dsi_pll_5nm";
|
|
vdda-0p9-supply = <&L5B>;
|
|
qcom,dsi-pll-ssc-en;
|
|
qcom,dsi-pll-ssc-mode = "down-spread";
|
|
qcom,platform-strength-ctrl = [55 03
|
|
55 03
|
|
55 03
|
|
55 03
|
|
55 00];
|
|
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
|
qcom,platform-lane-config = [00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 0a 0a
|
|
00 00 8a 8a];
|
|
qcom,phy-supply-entries {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
qcom,phy-supply-entry@0 {
|
|
reg = <0>;
|
|
qcom,supply-name = "vdda-0p9";
|
|
qcom,supply-min-voltage = <880000>;
|
|
qcom,supply-max-voltage = <880000>;
|
|
qcom,supply-enable-load = <37550>;
|
|
qcom,supply-disable-load = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|